A Logical Circuit Optimization in Balancing Delay and Energy Consumption

The fast-developing chip manufacturing technique and scaling of transistors allow us to fit more transistors on a small chip. The scaling down process, however, is facing a challenge. The smaller transistors are, the more influential quantum channeling and silicon atom size limit become. To improve efficiency, the solution of scaling down is no longer an option. Therefore, to further improve the efficiency of a chip without scaling down transistors, this paper presents a combinational circuit and focuses on an optimization approach where energy consumption is reduced in exchange for increasing delay. By adjusting the size of transistors, energy is saved while maintaining delay to an acceptable range. This approach manages to reduce energy consumption by about 56% while increasing delay by 50%. This paper represents one of many possible approaches that researchers had and has been working on and this tradeoff can benefit some circuit designs depending on the circuit’s purpose and hope to bring some insights on further optimization.