Systematic CXL Memory Characterization and Performance Analysis at Scale

dc.contributor.authorLiu, Jinshuen
dc.contributor.authorHadian, Hamiden
dc.contributor.authorWang, Yuyueen
dc.contributor.authorBerger, Danielen
dc.contributor.authorNguyen, Marieen
dc.contributor.authorJian, Xunen
dc.contributor.authorNoh, Samen
dc.contributor.authorLi, Huaichengen
dc.date.accessioned2025-04-04T12:14:10Zen
dc.date.available2025-04-04T12:14:10Zen
dc.date.issued2025-03-30en
dc.date.updated2025-04-01T07:47:43Zen
dc.description.abstractCompute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (Spa) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.en
dc.description.versionPublished versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.doihttps://doi.org/10.1145/3676641.3715987en
dc.identifier.urihttps://hdl.handle.net/10919/125147en
dc.language.isoenen
dc.publisherACMen
dc.rightsIn Copyrighten
dc.rights.holderThe author(s)en
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.titleSystematic CXL Memory Characterization and Performance Analysis at Scaleen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten

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