Systematic CXL Memory Characterization and Performance Analysis at Scale
dc.contributor.author | Liu, Jinshu | en |
dc.contributor.author | Hadian, Hamid | en |
dc.contributor.author | Wang, Yuyue | en |
dc.contributor.author | Berger, Daniel | en |
dc.contributor.author | Nguyen, Marie | en |
dc.contributor.author | Jian, Xun | en |
dc.contributor.author | Noh, Sam | en |
dc.contributor.author | Li, Huaicheng | en |
dc.date.accessioned | 2025-04-04T12:14:10Z | en |
dc.date.available | 2025-04-04T12:14:10Z | en |
dc.date.issued | 2025-03-30 | en |
dc.date.updated | 2025-04-01T07:47:43Z | en |
dc.description.abstract | Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (Spa) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL. | en |
dc.description.version | Published version | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.doi | https://doi.org/10.1145/3676641.3715987 | en |
dc.identifier.uri | https://hdl.handle.net/10919/125147 | en |
dc.language.iso | en | en |
dc.publisher | ACM | en |
dc.rights | In Copyright | en |
dc.rights.holder | The author(s) | en |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
dc.title | Systematic CXL Memory Characterization and Performance Analysis at Scale | en |
dc.type | Article - Refereed | en |
dc.type.dcmitype | Text | en |