Intelligent circuit recognition for VLSI layout verification

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dc.contributor.authorGriffin, Glennen
dc.contributor.committeechairTront, Joseph G.en
dc.contributor.committeememberMidkiff, Scott F.en
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:34:56Zen
dc.date.adate2010-04-27en
dc.date.available2014-03-14T21:34:56Zen
dc.date.issued1993-04-05en
dc.date.rdate2010-04-27en
dc.date.sdate2010-04-27en
dc.description.abstractThe ability to extract higher level information from a circuit netlist is useful for VLSI layout verification. An extracted gate level description may be used as input to a gate level simulator for analysis or alternatively may be used as input to a rule-based expert system that performs verification checking at a higher level of abstraction. As a VLSI design evolves it is continually checked for correctness. This implies that the extraction of higher level information is a recurring activity and should be performed as efficiently as possible. This paper describes an alternative method that uses intelligence to quicken the extraction process and compares this method's performance to a more common method.en
dc.description.degreeMaster of Scienceen
dc.format.extentiv, 68 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-04272010-020102en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-04272010-020102/en
dc.identifier.urihttp://hdl.handle.net/10919/42309en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V851_1993.G754.pdfen
dc.relation.isformatofOCLC# 28602404en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V851 1993.G754en
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Design and constructionen
dc.titleIntelligent circuit recognition for VLSI layout verificationen
dc.typeMaster's projecten
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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