Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method

dc.contributor.authorWang, Bixuanen
dc.contributor.authorZhang, Ruizheen
dc.contributor.authorSong, Qihaoen
dc.contributor.authorWang, Hengyuen
dc.contributor.authorHe, Quanboen
dc.contributor.authorLi, Qiangen
dc.contributor.authorUdrea, Florinen
dc.contributor.authorZhang, Yuhaoen
dc.date.accessioned2024-01-31T18:16:54Zen
dc.date.available2024-01-31T18:16:54Zen
dc.date.issued2024-01en
dc.description.abstractThe small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the DC bias stress or pulse I-V method, neither of which resembles the gate voltage (VGS) overshoot waveform in practical converters. This work develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like VGS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BVDYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive VGS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the VGS peak value and little dependence on the switching frequency. More interestingly, the gate's BVDYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 oC and 100 kHz, the VGS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.en
dc.description.sponsorshipThis work was supported in part by the Power Management Consortium of the Center for Power Electronics Systems at Virginia Tech and in part by the National Science Foundation under Grants ECCS-2202620, ECCS-2036740, and ECCS-2045001.en
dc.description.versionAccepted versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationBixuan Wang, Ruizhe Zhang, Qihao Song, Hengyu Wang, Quanbo He, Qiang Li, Florin Udrea, and Yuhao Zhang, “Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method,” in IEEE Transactions on Power Electronics (Early Access), doi: 10.1109/TPEL.2024.3355042.en
dc.identifier.urihttps://hdl.handle.net/10919/117767en
dc.language.isoenen
dc.publisherIEEEen
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subjectGaN HEMTen
dc.subjectgateen
dc.subjectreliabilityen
dc.subjectlifetimeen
dc.subjectrobustnessen
dc.subjectspikeen
dc.subjectringingen
dc.subjectbreakdown inductive power switchingen
dc.titleGate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Methoden
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten

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