Low-cost 3D flip-chip packaging technology for integrated power electronics modules
| dc.contributor.assignee | Virginia Tech Intellectual Properties, Inc. | en |
| dc.contributor.inventor | Lu, Guo-Quan | en |
| dc.contributor.inventor | Liu, Xingsheng | en |
| dc.date.accessed | 2016-08-19 | en |
| dc.date.accessioned | 2016-08-24T17:54:18Z | en |
| dc.date.available | 2016-08-24T17:54:18Z | en |
| dc.date.filed | 2000-09-13 | en |
| dc.date.issued | 2002-08-27 | en |
| dc.description.abstract | Resistance and parasitic inductance resulting from interconnection of semiconductor chips in power modules are reduced to negligible levels by a robust structure which completely avoids use of wire bonds through use of ball bonding and flip-chip manufacturing processes, possibly in combination with chip scale packaging and hourglass shaped stacked solder bumps of increased compliance and controlled height/shape. Turn-off voltage overshoot is reduced to about one-half or less than a comparable wire bond packaged power module. Hourglass shaped solder bumps provide increased compliance and reliability over much increased numbers of thermal cycles over wide temperature excursions. | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.applicationnumber | 9661376 | en |
| dc.identifier.patentnumber | 6442033 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/72454 | en |
| dc.identifier.url | http://pimg-fpiw.uspto.gov/fdd/33/420/064/0.pdf | en |
| dc.language.iso | en_US | en |
| dc.publisher | United States Patent and Trademark Office | en |
| dc.subject.cpc | H01L23/5385 | en |
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| dc.title | Low-cost 3D flip-chip packaging technology for integrated power electronics modules | en |
| dc.type | Patent | en |
| dc.type.dcmitype | Text | en |
| dc.type.patenttype | utility | en |
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