Low-cost 3D flip-chip packaging technology for integrated power electronics modules

dc.contributor.assigneeVirginia Tech Intellectual Properties, Inc.en
dc.contributor.inventorLu, Guo-Quanen
dc.contributor.inventorLiu, Xingshengen
dc.date.accessed2016-08-19en
dc.date.accessioned2016-08-24T17:54:18Zen
dc.date.available2016-08-24T17:54:18Zen
dc.date.filed2000-09-13en
dc.date.issued2002-08-27en
dc.description.abstractResistance and parasitic inductance resulting from interconnection of semiconductor chips in power modules are reduced to negligible levels by a robust structure which completely avoids use of wire bonds through use of ball bonding and flip-chip manufacturing processes, possibly in combination with chip scale packaging and hourglass shaped stacked solder bumps of increased compliance and controlled height/shape. Turn-off voltage overshoot is reduced to about one-half or less than a comparable wire bond packaged power module. Hourglass shaped solder bumps provide increased compliance and reliability over much increased numbers of thermal cycles over wide temperature excursions.en
dc.format.mimetypeapplication/pdfen
dc.identifier.applicationnumber9661376en
dc.identifier.patentnumber6442033en
dc.identifier.urihttp://hdl.handle.net/10919/72454en
dc.identifier.urlhttp://pimg-fpiw.uspto.gov/fdd/33/420/064/0.pdfen
dc.language.isoen_USen
dc.publisherUnited States Patent and Trademark Officeen
dc.subject.cpcH01L23/5385en
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dc.titleLow-cost 3D flip-chip packaging technology for integrated power electronics modulesen
dc.typePatenten
dc.type.dcmitypeTexten
dc.type.patenttypeutilityen
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