Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
| dc.contributor.assignee | Virginia Tech Intellectual Properties, Inc. | en |
| dc.contributor.inventor | Athanas, Peter M. | en |
| dc.contributor.inventor | Bittner, Jr., Ray A. | en |
| dc.date.accessed | 2016-08-19 | en |
| dc.date.accessioned | 2016-08-24T17:54:00Z | en |
| dc.date.available | 2016-08-24T17:54:00Z | en |
| dc.date.filed | 1996-09-16 | en |
| dc.date.issued | 1998-10-27 | en |
| dc.description.abstract | Higher performance is gained through a new architecture which implements a new method of computational resource allocation, utilization and programming based on the concept of Worm-hole Run-Time Reconfiguration (RTR). A stream-driven Worm-hole RTR methodology extends contemporary data-flow paradigms to utilize the dynamic creation of operators and pathways, based upon stream processing in which parcels of data move through custom created pathways and interact with other parcels to achieve the desired computation. These parcels independently allocate the necessary computing resources and data paths as they navigate through the platform. The Worm-hole RTR platform consists of a large number of configurable functional units that perform the custom computations and rich, configurable interconnection pathways between the functional units. Once a computational pathway has been established (sensitized) by the head of the stream parcel, data are processed through the pathway with zero overhead. All ports entering the computing platform serve both to configure operations and pathways and to pass computational data streams. As a result, programming and configuration is not limited to a single port. Configuration through multiple independent ports allows greater concurrency, faster reconfiguration, and fewer computational dependencies, all with relatively low cost in silicon. | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.applicationnumber | 8714348 | en |
| dc.identifier.patentnumber | 5828858 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/72370 | en |
| dc.identifier.url | http://pimg-fpiw.uspto.gov/fdd/58/288/058/0.pdf | en |
| dc.language.iso | en_US | en |
| dc.publisher | United States Patent and Trademark Office | en |
| dc.subject.cpc | G06F15/7867 | en |
| dc.subject.cpc | G06F15/17343 | en |
| dc.subject.cpc | G06F15/17381 | en |
| dc.subject.uspc | 710/317 | en |
| dc.subject.uspcother | 710/104 | en |
| dc.title | Worm-hole run-time reconfigurable processor field programmable gate array (FPGA) | en |
| dc.type | Patent | en |
| dc.type.dcmitype | Text | en |
| dc.type.patenttype | utility | en |
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