High temperature electrode-barriers for ferroelectric and other capacitor structures
dc.contributor.assignee | Virginia Tech Intellectual Properties, Inc. | en |
dc.contributor.assignee | Sharp Kabushiki Kaisha | en |
dc.contributor.inventor | Desu, Seshu B. | en |
dc.contributor.inventor | Vijay, Dilip P. | en |
dc.contributor.inventor | Bhatt, Hemanshu D. | en |
dc.contributor.inventor | Hwang, Yoo-Sang | en |
dc.date.accessed | 2016-08-19 | en |
dc.date.accessioned | 2016-08-24T17:53:57Z | en |
dc.date.available | 2016-08-24T17:53:57Z | en |
dc.date.filed | 1996-12-06 | en |
dc.date.issued | 1998-08-04 | en |
dc.description.abstract | A capacitor for use on silicon or other substrate has a multilayer electrode structure. In a preferred embodiment, a bottom electrode situated on the substrate has a bottom layer of Pt--Rh--O.sub.x, an intermediate layer of Pt--Rh, and a top layer of Pt--Rh--O.sub.x. A ferroelectric material such as PZT (or other material) is situated on the bottom electrode. A top electrode, preferably of identical composition as the bottom electrode, is situated on the opposite side of the ferroelectric from the bottom electrode. | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.applicationnumber | 8763011 | en |
dc.identifier.patentnumber | 5790366 | en |
dc.identifier.uri | http://hdl.handle.net/10919/72361 | en |
dc.identifier.url | http://pimg-fpiw.uspto.gov/fdd/66/903/057/0.pdf | en |
dc.language.iso | en_US | en |
dc.publisher | United States Patent and Trademark Office | en |
dc.subject.cpc | H01L28/60 | en |
dc.subject.uspc | 257/295 | en |
dc.subject.uspcother | 257/306 | en |
dc.subject.uspcother | 257/E21.011 | en |
dc.subject.uspcother | 361/305 | en |
dc.subject.uspcother | 361/311 | en |
dc.subject.uspcother | 361/313 | en |
dc.subject.uspcother | 361/322 | en |
dc.title | High temperature electrode-barriers for ferroelectric and other capacitor structures | en |
dc.type | Patent | en |
dc.type.dcmitype | Text | en |
dc.type.patenttype | utility | en |
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