Wires on demand: run-time communication synthesis for reconfigurable computing

dc.contributor.assigneeVirginia Tech Intellectual Properties, Inc.en
dc.contributor.inventorAthanas, Peter M.en
dc.contributor.inventorPatterson, Cameron D.en
dc.contributor.inventorDunham, Timothy G.en
dc.contributor.inventorBowen, John K.en
dc.contributor.inventorRice, Justin D.en
dc.contributor.inventorShelburne, Matthew T.en
dc.contributor.inventorPletri, Jorge Surisen
dc.contributor.inventorGraf, Jonathan P.en
dc.date.accessed2016-08-19en
dc.date.accessioned2016-08-24T17:55:03Zen
dc.date.available2016-08-24T17:55:03Zen
dc.date.filed2008-08-27en
dc.date.issued2011-03-08en
dc.description.abstractA method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.en
dc.format.mimetypeapplication/pdfen
dc.identifier.applicationnumber12199465en
dc.identifier.patentnumber7902866en
dc.identifier.urihttp://hdl.handle.net/10919/72661en
dc.identifier.urlhttp://pimg-fpiw.uspto.gov/fdd/66/028/079/0.pdfen
dc.language.isoen_USen
dc.publisherUnited States Patent and Trademark Officeen
dc.subject.cpcG06F17/5054en
dc.subject.uspc326/41en
dc.subject.uspcother326/38en
dc.titleWires on demand: run-time communication synthesis for reconfigurable computingen
dc.typePatenten
dc.type.dcmitypeTexten
dc.type.patenttypeutilityen

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