VHDL modeling of ASIC power dissipation

Abstract

Accurate predict of ASIC power diss ion is possible using VHDL. By using physical data types, timing and power estimations can be based on estimated typical fan-in and fan-out conditions and a pre-characterized circuit library. Actual load conditions can be back annotated to yield actual power dissipation. Methods to determine pattern sensitive and pattern insensitive power diss ion are presented. This approach uses the concept of load ports VHDL to permit self determining load conditions based on historical wiring data for a given technology.

Modeling techniques for VHDL circuit descriptions are developed that allow propagation delay, output rise and fall time, power dissipation be determined from VHDL event simulation. An example of an ALU such as the 74LS181 is presented.