A Task Scheduling Algorithm for Minimum Busiest Procesor Idle Time

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dc.contributor.authorHaddad, Emile K.en
dc.contributor.departmentComputer Scienceen
dc.date.accessioned2013-06-19T14:36:25Zen
dc.date.available2013-06-19T14:36:25Zen
dc.date.issued1993en
dc.description.abstractThis paper provides a heuristic to minimize the idle time of the busiest processor in a system in which the number of modules to be executed by every processor has been predetermined for a given precedence graph. Except for the busiest processor, the assignment of modules to the other processors is done as evenly as possible. Each of the modules involved is of unit size. An exhaustive enumeration solution of the problem is of NP-complete complexity. The heuristic presented in this paper is of polynomial time.en
dc.format.mimetypeapplication/pdfen
dc.identifierhttp://eprints.cs.vt.edu/archive/00000374/en
dc.identifier.sourceurlhttp://eprints.cs.vt.edu/archive/00000374/01/TR-93-32.pdfen
dc.identifier.trnumberTR-93-32en
dc.identifier.urihttp://hdl.handle.net/10919/19849en
dc.language.isoenen
dc.publisherDepartment of Computer Science, Virginia Polytechnic Institute & State Universityen
dc.relation.ispartofHistorical Collection(Till Dec 2001)en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.titleA Task Scheduling Algorithm for Minimum Busiest Procesor Idle Timeen
dc.typeTechnical reporten
dc.type.dcmitypeTexten

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