T-TER: Defeating A2 Trojans with Targeted Tamper-Evident Routing
| dc.contributor.author | Trippel, Timothy | en |
| dc.contributor.author | Shin, Kang | en |
| dc.contributor.author | Bush, Kevin | en |
| dc.contributor.author | Hicks, Matthew | en |
| dc.date.accessioned | 2023-08-02T17:46:21Z | en |
| dc.date.available | 2023-08-02T17:46:21Z | en |
| dc.date.issued | 2023-07-10 | en |
| dc.date.updated | 2023-08-01T07:57:59Z | en |
| dc.description.abstract | Since the inception of the Integrated Circuit (IC), the size of the transistors used to construct them has continually shrunk. While this advancement significantly improves computing capability, fabrication costs have skyrocketed. As a result, most IC designers must now outsource fabrication. Outsourcing, however, presents a security threat: comprehensive post-fabrication inspection is infeasible given the size of modern ICs, so it is nearly impossible to know if the foundry has altered the original design during fabrication (i.e., inserted a hardware Trojan). Defending against a foundry-side adversary is challenging because—even with as few as two gates— hardware Trojans can completely undermine software security. Researchers have attempted to both detect and prevent foundryside attacks, but all existing defenses are ineffective against additive Trojans with footprints of a few gates or less. We present Targeted Tamper-Evident Routing (T-TER), a layoutlevel defense against untrusted foundries, capable of thwarting the insertion of even the stealthiest hardware Trojans. T-TER is directed and routing-centric: it prevents foundry-side attackers from routing Trojan wires to, or directly adjacent to, security-critical wires by shielding them with guard wires. Unlike shield wires commonly deployed for cross-talk reduction, T-TER guard wires pose an additional technical challenge: they must be tamper-evident in both the digital (deletion attacks) and analog (move and jog attacks) domains. We address this challenge by developing a class of designed-in guard wires that are added to the design specifically to protect securitycritical wires. T-TER’s guard wires incur minimal overhead, scale with design complexity, and provide tamper-evidence against attacks. We implement automated tools (on top of commercial CAD tools) for deploying guard wires around targeted nets within an open-source System-on-Chip. Lastly, using an existing IC threat assessment toolchain, we show T-TER defeats even the stealthiest known hardware Trojan, with ≈ 1% overhead. | en |
| dc.description.version | Published version | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.doi | https://doi.org/10.1145/3579856.3582837 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/115962 | en |
| dc.language.iso | en | en |
| dc.publisher | ACM | en |
| dc.rights | In Copyright | en |
| dc.rights.holder | The author(s) | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.title | T-TER: Defeating A2 Trojans with Targeted Tamper-Evident Routing | en |
| dc.type | Article - Refereed | en |
| dc.type.dcmitype | Text | en |