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Browsing by Author "Raman, Sanjay"

Now showing 1 - 20 of 66
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    3D Micromachined Passive Components and Active Circuit Integration for Millimeter-wave Radar Applications
    Oliver, John Marcus (Virginia Tech, 2012-02-20)
    The development of millimeter-wave (30-300 GHz) sensors and communications systems has a long history of interest, spanning back almost six decades. In particular, mm-wave radars have applications as automotive radars, in remote atmospheric sensing applications, as landing radars for air and spacecraft, and for high precision imaging applications. Mm-wave radar systems have high angular accuracy and range resolution, and, while susceptible to atmospheric attenuation, are less susceptible to optically opaque conditions, such as smoke or dust. This dissertation document will present the initial steps towards a new approach to the creation of a mm-wave radar system at 94 GHz. Specifically, this dissertation presents the design, fabrication and testing of various components of a highly integrated mm-wave a 94 Ghz monopulse radar transmitter/receiver. Several architectural approaches are considered, including passive and active implementations of RF monopulse comparator networks. These architectures are enabled by a high-performance three-dimensional rectangular coaxial microwave transmission line technology known as PolyStrataTM as well as silicon-based IC technologies. A number of specific components are examined in detail, including: a 2x2 PolyStrata antenna array, a passive monopulse comparator network, a 94 GHz SiGe two-port active comparator MMIC, a 24 GHz RF-CMOS 4-port active monopulse comparator IC, and a series of V- and W-band corporate combining structures for use in transmitter power combining applications. The 94 GHz cavity-backed antennas based on a rectangular coaxial feeding network have been designed, fabricated, and tested. 13 dB gain for a 2 x 2 array, as well as antenna patterns are reported. In an effort to facilitate high-accuracy measurement of the antenna array, an E-probe transition to waveguide and PolyStrata diode detectors were also designed and fabricated. AW-band rectangular coaxial passive monopulse comparator with integrated antenna array and diode detectors have also been presented. Measured monopulse nulls of 31.4 dB in the ΔAZ plane have been demonstrated. 94-GHz SiGe active monopulse comparator IC and 24 GHz RF-CMOS active monopulse comparator RFIC designs are presented, including detailed simulations of monopulse nulls and performance over frequency. Simulations of the W-band SiGe active monopulse comparator IC indicate potential for wideband operation, with 30 dB monopulse nulls from 75-105 GHz. For the 24-GHz active monopulse comparator IC, simulated monopulse nulls of 71 dB and 68 dB were reported for the azimuthal and elevational sweeps. Measurements of these ICs were unsuccessful due to layout errors and incomplete accounting for parasitics. Simulated results from a series of rectangular coaxial power corporate power combining structures have been presented, and their relative merits discussed. These designs include 2-1 and 4-1 reactive, Wilkinson, and Gysel combiners at V- and W-band. Measured back-to-back results from Gysel combiners at 60 GHz included insertion loss of 0.13 dB per division for a 2-1 combination, and an insertion loss of 0.3 dB and 0.14 dB for "planar" and "direct" 4-1 combinations, respectively. At 94 GHz, a measured insertion loss of 0.1 dB per division has been presented for a 2-1 Gysel combination, using a back-to-back structure. Preliminary designs for a solid-state power amplifier (SSPA) structure have also been presented. Finally, two conceptual monopulse transceivers will be presented, as a vehicle for integrating the various components demonstrated in this dissertation.
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    5-6 GHz RFIC Front-End Components in Silicon Germanium HBT Technology
    Johnson, Daniel Austin (Virginia Tech, 2001-04-12)
    In 1997 the Federal Communications Commission (FCC) released 300 MHz of spectrum between 5-6 GHz designated the unlicensed national information infrastructure (U-NII) band. The intention of the FCC was to provide an unlicensed band of frequencies that would enable high-speed wireless local area networks (WLANs) and facilitate wireless access to the national information infrastructure with a minimum interference to other devices. Currently, there is a lack of cost-effective technologies for developing U-NII band components. With the commercial market placing emphasis on low cost, low power, and highly integrated implementations of RF circuitry, alternatives to the large and expensive distributed element components historically used at these frequencies are needed. Silicon Germanium (SiGe) BiCMOS technology represents one possible solution to this problem. The SiGe BiCMOS process has the potential for low cost since it leverages mature Si process technologies and can use existing Si fabrication infrastructure. In addition, SiGe BiCMOS processes offer excellent high frequency performance through the use of SiGe heterojunction bipolar transistors (HBTs), while coexisting Si CMOS offers compatibility with digital circuitry for high level 'system-on-a-chip' integration. The work presented in this thesis focuses on the development of a SiGe RFIC front-end for operation in the U-NII bands. Specifically, three variants of a packaged low noise amplifier (LNA) and a packaged active x2 sub-harmonic mixer (SHM) have been designed, simulated and measured. The fabrication of the Rifts was through the IBM SiGe foundry; the packaging was performed by RF Micro devices. The mixer and LNA designs were fabricated on separate die, packaged individually, and on-chip matched to a 50 ohm system so they could be fully characterized. Measurements were facilitated in a coaxial system using standard FR4 printed circuit boards. The LNA designs use a single stage, cascoded topology. The input ports are impedance matched using inductive emitter degeneration through bondwires to ground. One version of the LNA uses an shunt inductor/series capacitor output match while the other two variation use a series inductor output match. Gain, isolation, match, linearity and noise figure (NF) were used to characterize the performance of the LNAs in the 5 - 6 GHz frequency band. The best LNA design has a maximum gain of 9 dB, an input VSWR between 1.6:1 and 2:1, an output match between 1.7:1 and 3.6:1, a NF better than 3.9 dB and an input intercept point (IIP3) greater than 5.4 dBm. The LNA operates from a 3.3 V supply voltage and consumes 4 mA of current. The SHM is an active, double-balance mixer that achieves x2 sub-harmonic mixing through two quadrature (I/Q) driven, stacked Gilbert-cell switching stages. Single-ended-to-differential conversion, buffering and I/Q phase separation of the LO signal are integrated on-chip. Measurements were performed to find the optimal operating range for the mixer, and the mixer was characterized under these sets of conditions. It was found that the optimal performance of the mixer occurs at an IF of 250-450 MHz and an LO power of -5 dBm. Under these conditions, the mixer has a measured conversion gain of 9.3 dB, a P_1-dB of -15.7 dBm and an 2LO/RF isolation greater than 35 dB at 5.25 GHz. At 5.775 GHz, the conversion gain is 7.7 dB, the P1-dB is -15.0 dBm, and the isolation is greater than 35 dB. The mixer core consumes 9.5 mA from a 5.0 V supply voltage. This work is sponsored by RF Microdevices (RFMD)through the CWT affiliate program.The author was supported under a Bradley Foundation fellowship.
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    A 5-6 Ghz Silicon-Germanium Vco With Tunable Polyphase Outputs
    Sanderson, David Ivan (Virginia Tech, 2003-04-24)
    In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit.
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    A 60 Ghz Mmic 4x Subharmonic Mixer
    Chapman, Michael Wayne (Virginia Tech, 2000-10-31)
    In this modern age of information, the demands on data transmission networks for greater capacity, and mobile accessibility are increasing drastically. The increasing demand for mobile access is evidenced by the proliferation of wireless systems such as mobile phone networks and wireless local area networks (WLANs). The frequency range over which an oxygen resonance occurs in the atmosphere (~58-62 GHz) has received recent attention as a possible candidate for secure high-speed wireless data networks with a potentially high degree of frequency reuse. A significant challenge in implementing data networks at 60 GHz is the manufacture of low-cost RF transceivers capable of satisfying the system requirements. In order to produce transceivers that meet the additional demands of high-volume, mobility, and compactness, monolithic millimeter wave integrated circuits (MMICs) offer the most practical solution. In the design of radio tranceivers with a high degree of integration, the receiver front-end is typically the most critical component to overall system performance. High-performance low-noise amplifiers (LNAs) are now realizable at frequencies in excess of 100 GHz, and a wide variety of mixer topologies are available that are capable of downconversion from 60 GHz. However, local oscillators (LOs) capable of providing adequate output power at mm-wave frequencies remain bulky and expensive. There are several techniques that allow the use of a lower frequency microwave LO to achieve the same RF downconversion. One of these is to employ a subharmonic mixer. In this case, a lower frequency LO is applied and the RF mixes with a harmonic multiple of the LO signal to produce the desired intermediate frequency (IF). The work presented in this thesis will focus on the development of a GaAs MMIC 4-X subharmonic mixer in Finite Ground Coplanar (FGC) technology for operation at 60 GHz. The mixer topology is based on an antiparallel Schottky diode pair. A discussion of the mechanisms behind the operation of this circuit and the methods of practical implementation is presented. The FGC transmission lines and passive tuning structures used in mixer implementation are characterized with full-wave electromagnetic simulation software and 2-port vector network analyzer measurements. A characterization of mixer performance is obtained through simulations and measurement. The viability of this circuit as an alternative to other high-frequency downconversion schemes is discussed. The performance of the actual fabricated MMIC is presented and compared to currently available 60 GHz mixers. One particular MMIC design exhibits an 11.3 dB conversion loss at an RF of 58.5 GHz, an LO frequency of 14.0 GHz, and an IF of 2.5 GHz. This represents excellent performance for a 4X Schottky diode mixer at these frequencies. Finally, recommendations toward future research directions in this area are made.
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    Air Surveillance for Smart Landing Facilities in the Small Aircraft Transportation System
    Shea, Eric Joseph (Virginia Tech, 2002-04-18)
    The Small Aircraft Transportation System (SATS) is a partnership among various organizations including NASA, the FAA, US aviation industry, state and local aviation officials, and universities. The program objectives are intend to reduce travel times by providing high-speed, safe travel alternatives by making use of small aircraft and underused small airports throughout the nation. A major component of the SATS program is the Smart Landing Facility (SLF). The SLF is a small airport that has been upgraded to handle SATS traffic. One of the services needed at SLFs is air surveillance of the airspace surrounding it. This thesis researches the different surveillance techniques available for use at the SLFs. The main focuses of this paper are an evaluation of the Traffic Alert and Collision Avoidance System (TCAS) when used as a ground sensor at SLFs and the design of a Position and Identification Reporting Beacon (PIRB). The use of the TCAS ground sensor is modeled in Matlab and the results of that model are discussed. The PIRB is a new system that can be used in conjunction with the Automatic Dependent Surveillance-Broadcast (ADS-B) system or independently to provide position information for all aircraft using GPS based positioning.
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    Analog fourier transform channelizer and OFDM receiver
    (United States Patent and Trademark Office, 2010-09-21)
    An OFDM receiver having an analog multiplier based I-Q channelizing filter, samples and holds consecutive analog I-Q samples of an I-Q baseband, the I-Q basebands having OFDM sub-channels. A lattice of analog I-Q multipliers and analog I-Q summers concurrently receives the held analog I-Q samples, performs analog I-Q multiplications and analog I-Q additions to concurrently generate a plurality of analog I-Q output signals, representing an N-point discrete Fourier transform of the held analog samples, the I-Q signals having relative phase and magnitude representing bits in the OFDM sub-channels. The phase and magnitude may represent QPSK. Optionally, a phase shift decoder receives the analog transform I-Q output signals and generates a corresponding binary bit data.
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    An Analog/Mixed Signal FFT Processor for Ultra-Wideband OFDM Wireless Transceivers
    Lehne, Mark (Virginia Tech, 2008-07-28)
    As Orthogonal Frequency Division Multiplexing (OFDM) becomes more prevalent in new leading-edge data rate systems processing spectral bandwidths beyond 1 GHz, the required operating speed of the baseband signal processing, specifically the Analog- to-Digital Converter (ADC) and Fast Fourier Transform (FFT) processor, presents significant circuit design challenges and consumes considerable power. Additionally, since Ultra-WideBand (UWB) systems operate in an increasingly crowded wireless environment at low power levels, the ability to tolerate large blocking signals is critical. The goals of this work are to reduce the disproportionately high power consumption found in UWB OFDM receivers while increasing the receiver linearity to better handle blockers. To achieve these goals, an alternate receiver architecture utilizing a new FFT processor is proposed. The new architecture reduces the volume of information passed through the ADC by moving the FFT processor from the digital signal processing (DSP) domain to the discrete time signal processing domain. Doing so offers a reduction in the required ADC bit resolution and increases the overall dynamic range of the UWB OFDM receiver. To explore design trade-offs for the new discrete time (DT) FFT processor, system simulations based on behavioral models of the key functions required for the processor are presented. A new behavioral model of the linear transconductor is introduced to better capture non-idealities and mismatches. The non-idealities of the linear transconductor, the largest contributor of distortion in the processor, are individually varied to determine their sensitivity upon the overall dynamic range of the DT FFT processor. Using these behavioral models, the proposed architecture is validated and guidelines for the circuit design of individual signal processing functions are presented. These results indicate that the DT FFT does not require a high degree of linearity from the linear transconductors or other signal processing functions used in its design. Based on the results of the system simulations, a prototype 8-point DT FFT processor is designed in 130 nm CMOS. The circuit design and layout of each of the circuit functions; serial-to-parallel converter, FFT signal flow graph, and clock generation circuitry is presented. Subsequently, measured results from the first proof-of-concept IC are presented. The measured results show that the architecture performs the FFT required for OFDM demodulation with increased linearity, dynamic range and blocker handling capability while simultaneously reducing overall receiver power consumption. The results demonstrate a dynamic range of 49 dB versus 36 dB for the equivalent all-digital signal processing approach. This improvement in dynamic range increases receiver performance by allowing detection of weak sub-channels attenuated by multipath. The measurements also demonstrate that the processor rejects large narrow-band blockers, while maintaining greater than 40 dB of dynamic range. The processor enables a 10x reduction in power consumption compared to the equivalent all digital processor, as it consumes only 25 mWatts and reduces the required ADC bit depth by four bits, enabling application in hand-held devices. Following the success of the first proof-of-concept IC, a second prototype is designed to incorporate additional functionality and further demonstrate the concept. The second proof-of-concept contains an improved version of the serial-to-parallel converter and clock generation circuitry with the additional function of an equalizer and parallel- to-serial converter. Based on the success of system level behavioral simulations, and improved power consumption and dynamic range measurements from the proof-of-concept IC, this work represents a contribution in the architectural development and circuit design of UWB OFDM receivers. Furthermore, because this work demonstrates the feasibility of discrete time signal processing techniques at 1 GSps, it serves as a foundation that can be used for reducing power consumption and improving performance in a variety of future RF/mixed-signal systems.
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    The Analysis and Design of Phase-tunable Low-Power Low-Phase-Noise I/Q Signal Sources for Analog Phase Calibrated Transceivers
    Chamas, Ibrahim (Virginia Tech, 2008-06)
    Due to the demand for low-cost, small-form factor and large-scale integration of system-on-chip wireless transceivers, the image-reject, zero-IF and low-IF receiver architectures have become the main topologies used in mainstream wireless communication systems. Consequently, signal sources with quadrature phase outputs [quadrature oscillators (QOs)] are therefore essential, and their phase noise, driving capability, tuning range, oscillation frequency, and power consumption have a major impact on the overall receiver performance. Additionally, it is required that the QO synthesize precise I/Q waveforms across the signal bandwidth over process, voltage, and temperature variations for adequate image-rejection and signal modulation/demodulation. While the use of symmetrical layout and large inter-digitated devices minimize both systematic and random mismatches, this solution alone may not succeed in achieving the stringent performance requirements dictated by modern wireless standards particularly as the technology scales into the sub-100nm regime, necessitating both phase and gain calibration of the mismatched I/Q channels post-fabrication. Given the necessity for precise RF quadrature signal synthesis, the goal of this work is to investigate low-power low-phase-noise quadrature oscillator (QVCO) topologies with an integrated phase calibration feature. The first part of this work focuses on the analysis and modeling of cross-coupled LC QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, design trade-offs, phase-noise performance, effect of including phase shift in the coupling paths, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. Particularly, we introduce the concept of an effective core and coupling transconductances to explain various oscillator properties. Additionally, a new incremental circuit element — the quadrature resistance — is introduced to evaluate the effect of coupling on the open-loop quality factor and hence on the oscillator phase noise performance. Mechanisms affecting the mode selectivity are identified and modeled. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based on the disconnected-source parallel-coupled LC QVCO topology. The phase-tunable LC QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the relative amplitude error or consuming additional power or chip area. Additionally, in restoring the phase balance, it is observed that the proposed method restores the phase noise performance to its optimal value which presents a potential advantage over classical calibration techniques. Time domain measurements performed on a 5 GHz prototype show that I/Q signals with phase error up to ~±30°, beyond which the VCO cores are unlocked, can be driven to perfect quadrature phase. The PT-QVCO can be tuned from 3.87-4.45 GHz at the negative mode and 4.4-5.4 GHz at the positive mode, a total of ~1.5 GHz. The fabricated circuit including pad structures occupies an area of 1.1x0.7 mm² and drains 18mW (excluding buffer circuits) from a 1.8 V supply voltage. The third part of this work introduces a new low-power, low-phase-noise super harmonic injection-coupled LC QVCO (IC-QVCO) topology. Analysis of the waveform accuracy reveals an inverse dependence of the quadrature error on the tank quality factor thus allowing circuit optimization for both low phase noise and precise quadrature synthesis. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-σ variation in the device parameters. An X-band IC-QVCO prototype with a TTF implemented in a 0.18μm RF CMOS process, achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz along the 9.0 to 9.6 GHz frequency tuning range while dissipating only 9mW from the 1.8V supply. The TTF reduces both the 1/f² and 1/f³ phase noise and calibrates the residual phase error within ±11° post-fabrication without affecting the relative amplitude error or the phase noise performance. The circuit performance compares favorably with recently published work. In the fourth part of this work, we explore the implementation of LC QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an MOS varactor and a digitally controlled switch capacitor array for frequency tuning, we propose an alternative frequency tuning technique based on the fundamental operation of LC QVCOs. The off-resonance operation, which is defined by the coupling network, suggests varying the coupling current to achieve frequency tuning. In essence, by modifying the bias current of the coupling transistors (GMc-tuning), a wide and linear frequency tuning range can be achieved. Extensive simulation results of a 60 GHz prototype, implemented in a 90 nm commercial RF CMOS process, demonstrates a 5 GHz of frequency tuning range (57.5 GHz → 62.5 GHz), a tuning sensitivity of 1GHz/mA, and a 4dB improvement in the phase noise compared to a varactor solution. Finally, the Appendix includes recent research work on the analysis and design of gm-boosted common-gate low-noise amplifiers (CG-LNAs). While this topic seems to diverge from the main theme of the dissertation, we believe that the comprehensive analysis and the originality of the circuit design introduced in this work are worth acknowledging.
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    Applications of Non-linearities in RF MEMS Switches and Resonators
    Vummidi Murali, Krishna Prasad (Virginia Tech, 2015-04-06)
    The 21st century is emerging into an era of wireless ubiquity. To support this trend, the RF (Radio Frequency) front end must be capable of processing a range of wireless signals (cellular phone, data connectivity, broadcast TV, GPS positioning, etc.) spanning a total bandwidth of nearly 6 GHz. This warrants the need for multi-band/multi-mode radio architectures. For such architectures to satisfy the constraints on size, battery life, functionality and cost, the radio front-end must be made reconfigurable. RF-MEMS (RF Micro-Electro-Mechanical Systems) are seen as an enabling technology for such reconfigurable radios. RF-MEMS mainly include micromechanical switches (used in phase shifters, switched capacitor banks, impedance tuners etc.) and micromechanical resonators (used in tunable filters, oscillators, reference clocks etc.). MEMS technology also has the potential to be directly integrated into CMOS (Complementary metal-oxide semiconductor) ICs (Integrated Circuits) leading to further potential reductions of cost and size. However, RF-MEMS face challenges that must be addressed before they can gain widespread commercial acceptance. Relatively low switching speed, power handling, and high-voltage drive are some of the key issues in MEMS switches. Phase noise influenced by non-linearities, need for temperature compensation (especially Si based resonators), large start-up times, and aging are the key issues in Si MEMS Resonators. In this work potential solutions are proposed to address some of these key issues, specifically the reduction of high voltage drives in switches and the reduction of phase noise in MEMS resonators for timing applications. MEMS devices that are electrostatically actuated exhibit significant non-linearities. The origins of the non-linearities are both electrical (electrostatic actuation) and mechanical (dimensions and material properties). The influence of spring non-linearities (cubic and quadratic) on the performance of switches and resonators are studied. Gold electroplated fixed-fixed beams were fabricated to test the phenomenon of dynamic (or resonant) pull-in in shunt switches. The dynamic pull-in phenomenon was also tested on commercially fabricated lateral switches. It is shown that the resonant pull-in technique reduces the overall voltage required to actuate the switch. There is an additional reduction of total actuation voltage possible via applying an AC actuation signal at the correct non-linear resonant frequency. The demonstrated best case savings from operating at the non-linear resonanceis 50 % (for the lateral switch) and 60 % (for the vertical switch) as compared to 25 % and 40 % respectively using a fixed frequency approach. However, the timing response for resonant pull-in has been experimentally shown to be slower than the static actuation. To reduce the switching time, a shifted-frequency method is proposed where the excitation frequency is shifted up or down by a discrete amount 'Ω after a brief hold time. It was theoretically shown that the shifted-frequency method enables a minimum realizable switching time comparable to the static switching time for a given set of actuation frequencies. The influence of VDC on the effective non-linearities of a fixed-fixed beam is also studied. Based on the dimensions of the resonator and the type of resonance there is a certain VDC,Lin where the response is near linear (S ' 0). In the near-linear domain, the dynamic pull-in is the only upper bound to the amplitude of vibrations, and hence the amplitude of output current, thereby maximizing the power handling capacity of the resonator. Apart from maximizing the output current, it is essential to reduce the amplitude and phase variations of the displacement response which are due to noise mixing into frequency of interest, and are eventually manifested as output phase noise due to capacitive current nonlinearity. Two major aliasing schemes were analyzed and it was shown that the capacitive force non-linearity is the major source of mixing that causes the up-conversion of 1/f frequency into signal sidebands. The resonator's periodic response (displacement) is defined by a set of two first- order nonlinear ordinary differential equations that describe the modulation of amplitude and phase of the response. Frequency response curves of amplitude and frequency are determined from these modulation equations. The zero slope point on the amplitude resonance curve is the peak of the resonance curve where the phase ('dc) of the response is ±π/2. For a strongly non-linear system, the resonance curves are skewed based on the amount of total non-linearity S. For systems that are strongly non-linear, the best region to operate the resonator is the fixed point that correspond to infinite slope ('dc = ±2π/3) in the frequency response of the system. The best case phase noise response was analytically developed for such a fixed point. Theoretically at this fixed point, phase noise will have contributions only from 1/f noise and not from 1/f2 and 1/f3. The resonators phase can be set by controlling the rest of the phase in the loop such that the total phase around the loop is zero or 2π. In addition, this work has also developed an analytical model for a lateral MEMS switch fabricated in a commercial foundry that has the potential to be processed as MEMS on CMOS. This model accounts for trapezoidal cross sections of the electrodes and springs and also models electrostatic fringing as a function of the moving gap. The analytical model matches closely with the Finite Element (FEA) model.
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    Bidirectional DC-DC Power Converter Design Optimization, Modeling and Control
    Zhang, Junhong (Virginia Tech, 2008-01-30)
    In order to increase the power density, the discontinuous conducting mode (DCM) and small inductance is adopted for high power bidirectional dc-dc converter. The DCM related current ripple is minimized with multiphase interleaved operation. The turn-off loss caused by the DCM induced high peak current is reduced by snubber capacitor. The energy stored in the capacitor needs to be discharged before device is turned on. A complementary gating signal control scheme is employed to turn on the non-active switch helping discharge the capacitor and diverting the current into the anti-paralleled diode of the active switch. This realizes the zero voltage resonant transition (ZVRT) of main switches. This scheme also eliminates the parasitic ringing in inductor current. This work proposes an inductance and snubber capacitor optimization methodology. The inductor volume index and the inductor valley current are suggested as the optimization method for small volume and the realization of ZVRT. The proposed capacitance optimization method is based on a series of experiments for minimum overall switching loss. According to the suggested design optimization, a high power density hardware prototype is constructed and tested. The experimental results are provided, and the proposed design approach is verified. In this dissertation, a general-purposed power stage model is proposed based on complementary gating signal control scheme and derived with space-state averaging method. The model features a third-order system, from which a second-order model with resistive load on one side can be derived and a first-order model with a voltage source on both sides can be derived. This model sets up a basis for the unified controller design and optimization. The Δ-type model of coupled inductor is introduced and simplified to provide a more clearly physical meaning for design and dynamic analysis. These models have been validated by the Simplis ac analysis simulation. For power flow control, a unified controller concept is proposed based on the derived general-purposed power stage model. The proposed unified controller enables smooth bidirectional current flow. Controller is implemented with digital signal processing (DSP) for experimental verification. The inductor current is selected as feedback signal in resistive load, and the output current is selected as feedback signal in battery load. Load step and power flow step control tests are conducted for resistive load and battery load separately. The results indicate that the selected sensing signal can produce an accurate and fast enough feedback signal. Experimental results show that the transition between charging and discharging is very smooth, and there is no overshoot or undershoot transient. It presents a seamless transition for bidirectional current flow. The smooth transition should be attributed to the use of the complementary gating signal control scheme and the proposed unified controller. System simulations are made, and the results are provided. The test results have a good agreement with system simulation results, and the unified controller performs as expected.
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    A Comprehensive Investigation of New Planar Wideband Antennas
    Suh, Seong-Youp (Virginia Tech, 2002-07-29)
    Broadband wireless communications require wideband antennas to support large number of users and higher data rates. Desirable features of a wideband antenna are low-profile, dual-polarization and wide bandwidth in a compact size. Many existing wideband antennas are large in size and some have only circular polarization. On the other hand low-profile, dual-polarized antennas frequently have limited bandwidth. This dissertation reports on results from original research into several new wideband antennas. All are compact and planar, and many are low-profile and dual-polarized. Since 1994, Virginia Tech Antenna Group (VTAG) has performed research on the wideband, low-profile and dual-polarized antennas of compact size. This research resulted in the following antenna innovations: the Fourpoint, Fourtear, PICA (Planar Inverted Cone Antenna), diPICA (dipole PICA) and LPdiPICA (Low-Profile diPICA) antennas. They are all planar in geometry so one can easily construct them in a compact size. The antennas were characterized and investigated with extensive simulations and measurements. The computed and measured data demonstrates that some of the antennas appear to have the characteristics of the self-complementary antenna and most of the proposed antennas provide more than a 10:1 impedance bandwidth for a VSWR < 2. Patterns, however, are degraded at the high end of the frequency. Several tapered ground planes were proposed to improve the radiation pattern characteristics without degrading the impedance performance. A simulation result proposed a possibility of another antenna inventions providing 10:1 pattern bandwidth with the 10:1 impedance bandwidth. Research into wideband antennas demonstrated that the newly invented antennas are closely related each other and are evolved from a primitive element, PICA. Not only the comprehensive investigation but also a practical antenna design has been done for commercial base-station array antennas and to phased array antennas for government applications. This dissertation presents results of comprehensive investigation of new planar wideband antennas and its usefulness to the broadband wireless communications.
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    Cyberbiosecurity: An Emerging New Discipline to Help Safeguard the Bioeconomy
    Murch, Randall Steven; So, William K.; Buchholz, Wallace G.; Raman, Sanjay; Peccoud, Jean (2018-04-05)
    Cyberbiosecurity is being proposed as a formal new enterprise which encompasses cybersecurity, cyber-physical security and biosecurity as applied to biological and biomedical-based systems. In recent years, an array of important meetings and public discussions, commentaries and publications have occurred that highlight numerous vulnerabilities. While necessary first steps, they do not provide a systematized structure for effectively promoting communication, education and training, elucidation and prioritization for analysis, research, development, test and evaluation and implementation of scientific, technological, standards of practice, policy, or even regulatory or legal considerations for protecting the bioeconomy. Further, experts in biosecurity and cybersecurity are generally not aware of each other's domains, expertise, perspectives, priorities, or where mutually supported opportunities exist for which positive outcomes could result. Creating, promoting and advancing a new discipline can assist with formal, beneficial and continuing engagements. Recent key activities and publications that inform the creation of Cyberbiosecurity are briefly reviewed, as is the expansion of Cyberbiosecurity to include biomanufacturmg which is supported by a rigorous analysis of a biomanufacturmg facility. Recommendations are provided to initialize Cyberbiosecurity and place it on a trajectory to establish a structured and sustainable discipline, forum and enterprise.
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    Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies
    Ralston, Parrish Elaine (Virginia Tech, 2013-05-08)
    Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in laying out flip chip bond pads. Reduction in interconnect parasitics enables these interconnects to support broadband signals, therefore increasing the bandwidth capabilities of flip chip-assembled systems. Traditional flip chip designs provide mechanical and electrical connections from a top chip to a carrier substrate with rigid solder joints. For heterogeneous assemblies, flip chip connections suffer from thermo-mechanical failures caused by coefficient of thermal expansion mismatches. As an alternative, flexible flip chip interconnections incorporating a metal, which is liquid at room temperature, mitigates the possibility of such thermo-mechanical failures. Additionally, liquid metal, flip chip interconnections allow for room temperature assembly, simplifying assembly and rework processes. This dissertation focuses on the design and characterization of liquid metal interconnections, specifically using Galinstan, an alloy of gallium indium and tin, for the heterogeneous assembly of active monolithic microwave integrated circuits (MMICs) onto a CTE mismatched substrate. Carrier substrates designed for liquid metal transitions were fabricated on high resistivity Si and on three dimensional copper structures. The three dimensional copper structures were fabricated in the PolyStrata™ process. Individual MMIC chips were post-processed to mate with carrier substrates in a liquid metal, flip chip configuration. S-parameter measurements of prototype MMIC assemblies with liquid metal, flip chip interconnections showed an average transition loss of 0.7dB over the MMIC's frequency of operation (4.9 - 8.5 GHz). Passive assemblies were also fabricated to characterize the power and temperature performance of liquid metal transitions. Liquid metal interconnections show excellent power handling, maintaining consistent RF performance while transmitting 100W of continuous wave power for an hour. Liquid metal interconnections were also tested following 200 temperature cycles over the -140°C – 125°C range. A comparison of S parameter measurements taken before and after temperature cycling, over a frequency range of 10MHz - 40GHz showed no significant changes in performance. These passive assemblies were also used to develop a lumped element model of the interconnection which is useful for the verification the interconnection\'s performance and for comparison of liquid metal interconnection parasitic to wire bond and flip chip interconnect parasitics. The experimental results presented in this dissertation confirm that liquid metal interconnect are viable for wider use in military and commercial applications. In the future, additional environmental testing and further refinement of the processing flow, such as improved contact metallurgy, are needed to make this interconnect approach more viable for large volume manufacturing.
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    Design and Characterization of RFIC Voltage Controlled Oscillators in Silicon Germanium HBT and Submicron MOS Technologies
    Klein, Adam Sherman (Virginia Tech, 2003-09-11)
    Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered.
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    Design and Implementation of an Ultrabroadband Millimeter-Wavelength Vector Sliding Correlator Channel Sounder and In-Building Multipath Measurements at 2.5 & 60 GHz
    Anderson, Christopher R. (Virginia Tech, 2002-05-06)
    Over the past decade, the market for wireless service has grown at an unprecedented rate. The industry has grown from cellular phones and pagers to broadband and ultra-broadband (also called ultra-wideband) wireless services that can provide voice, data, and full-motion video in real time. This growing hunger for faster data rates and larger bandwidths has prompted a need for a deeper understanding of the wireless channels upon which these devices communicate. In order for the visions of real time full-motion video, multimedia, and high speed data delivery inherent in the 3rd and 4th generations of wireless communication standards to be fully realized, system design engineers must have a thorough understanding of the wireless channels upon which these devices operate. Additionally, for these networks to deliver their promised data rates, they must operate at very high microwave and millimeter-wave frequencies, where large segments of spectrum are readily obtained. Unfortunately, little is known about the propagation characteristics at these frequencies and bandwidths. As a consequence, there has been a significant demand for wireless test equipment that is capable of characterizing these new wireless channels. The objective of this research was to design and develop a wireless test instrument that can not only characterize these new wireless channels, but has the portability to be quickly and easily re-located to various measurement sites, as well as the flexibility to characterize a wide variety of frequencies and bandwidths in addition to the ultrawideband channels investigated in this work. This measurement system is also designed to be capable of characterizing both the magnitude and phase response of these wireless channels, which not only provides a more complete channel characteristic, but the potential capability to measure the Doppler spectrum introduced by a dynamic channel.
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    Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs
    Ralston, Parrish Elaine (Virginia Tech, 2008-12-12)
    There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0–40V) and high voltage (40–5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed.
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    Design of a Highly Linear 24-GHz LNA
    Elyasi, Hedieh (Virginia Tech, 2016-07-05)
    The increasing demand for high data rate devices and many applications in short range high speed communication, attract many RF IC designers to work on 24-GHz transceiver design. The Federal Communication Commission (FCC) also dedicates the unlicensed 24-GHz band for industrial, science, and medical applications to overcome the interference in overcrowded communications and have higher output signal power. LNA is the first building of the receiver and is a very critical building block for the overall receiver performance. The total NF and sensitivity of the receiver mainly depends on the LNAs NF that mandates a very low NF LNA design. Depending on its gain, the noise figure of the next stages can relax. However, the high gain of an LNA enforces the next stages to be more linear since they suffer from larger signal at their input stage and can get saturated easily. Apparently, designing high gain, low noise, and highly linear LNA is very stimulating. In this thesis, a wideband LNA with low noise figure and high linearity has been designed in 8XP 0.13-um SiGe BiCMOS IBM technology. The highlight of this design is proposing the peaking technique, which results in considerable linearity improvement. Loading the LNA with class AB amplifier, power gain experiences a peaking in high input signal swing levels. The next stager after the LNA is the buffer to provide isolation between the LNA and mixer, and also avoid loading of the LNA from the mixer. Instead of using popular emitter follower architecture, another circuit is proposed to have higher gain and linearity. This buffer has two separate out of phase inputs, coming from the LNA and are combined constructively at the output of the buffer. Since the frequency of this design is high, electromagnetic (EM) simulation for pads, interconnects, transmission lines, inductors, and coplanar transmission lines has been completed using Sonnet cad tool to consider all the parasitic and coupling effects. Considering all the EM effects, the LNA has 15 dB gain with 2.9 dB NF and -8.8 dBm input 1-dB compression point. The designed LNA is wideband, covering the frequency range of 12-GHz to 31-GHz. However, the designed LNA, has the capability of having higher gain at the expense of lower linearity and narrower frequency band using different control voltage. As an example peak gain of 29.3 dB at the 3-dB frequency range of 23.8 to 25.8-GHz can be achieved, having 2.3 dB noise figure and -17 dBm linearity.
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    Design of RF CMOS Power Amplifier for UWB Applications
    Jose, Sajay (Virginia Tech, 2004-12-10)
    Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications. However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task. Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals. This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply. In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design.
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    Design of Ultrawideband Digitizing Receivers for the VHF Low Band
    Taylor, David Wyatt (Virginia Tech, 2006-05-09)
    The next generation of receivers for applications such as radio astronomy, spectrum surveillance, and frequency-adaptive cognitive radio will require the capability to digitize very large bandwidths in the VHF low band (30 to 100 MHz). However, methodology for designing such a receiver is not well established. The difficulties of this design are numerous. There are various man-made interferers occupying this spectrum which can block desired signals or spectrum, either directly or through intermodulation. The receivers will typically use simple (i.e., narrowband) antennas, so the efficiency of power transfer to the preamplifier needs to be carefully considered. This thesis takes these design challenges into account and produces a seven step design methodology for direct sampling wideband digitizing receivers. The methodology is then demonstrated by example for three representative receivers. Finally, improvements to the analysis are suggested.
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    Design, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devices
    Collins, Gustina B. (Virginia Tech, 2006-06-05)
    A low-cost, low-temperature packaging concept is proposed for localized sealing and control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro- Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices require application specific packaging to facilitate their integration, provide protection from the environment, and control interactions with other circuitry. In order to integrate these devices into standard integrated circuit (IC) process flows and minimize damage due to post-fabrication steps, packaging is performed at the wafer level. In this work Indium and Silver are used to seal a monolithic localized hermetic pack- age. The cavity protecting the device is formed using standard lithography-based processing techniques. Metal walls are built up from the substrate and encapsulated by a glass or silicon lid to create a monolithic micro-hermetic package surrounding a predefined RF microsystem. The bond for the seal is then formed by rapid alloying of Indium and Silver using a temperature greater than that of the melting point of Indium. This ensures that the seal formed can subsequently function at temperatures higher than the melting temperature of pure Indium. This method offers a low-temperature bonding technique with thermal robustness suitable for wafer-level process integration. The ultimate goal is to create a seal in a vacuum environment. In this dissertation, design trade-offs made in wafer-level packaging are explained using thermo-mechanical stress and electrical performance simulations. Prototype passive microwave circuits are packaged using the developed packaging process and the performance of the fabricated circuits before and after packaging is analyzed. The effect of the package on coplanar waveguide structures are characterized by measuring scattering parameters and models are developed as a design tool for wafer-level package integration. The small scale of the localized package is expected to provide greater reliability over conventional full chip packages.