Browsing by Author "Steiner, Neil Joseph"

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    Autonomous Computing Systems
    Steiner, Neil Joseph (Virginia Tech, 2008-03-27)
    This work discusses autonomous computing systems, as implemented in hardware, and the properties required for such systems to function. Particular attention is placed on shifting the associated complexity into the systems themselves, and making them responsible for their own resources and operation. The resulting systems present simpler interfaces to their environments, and are able to respond to changes within themselves or their environments with little or no outside intervention. This work proposes a roadmap for the development of autonomous computing systems, and shows that their individual components can be implemented with present day technology. This work further implements a proof-of-concept demonstration system that advances the state-of-the-art. The system detects activity on connected inputs, and responds to the conditions without external assistance. It works from mapped netlists, that it dynamically parses, places, routes, configures, connects, and implements within itself, at the finest granularity available, while continuing to run. The system also models itself and its resource usage, and keeps that model synchronized with the changes that it undergoes—a critical requirement for autonomous systems. Furthermore, because the system assumes responsibility for its resources, it is able to dynamically avoid resources that have been masked out, in a manner suitable for defect tolerance.
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    Investigation of Non-Traditional Applications of the Physical Level in Reconfigurable Computing
    Couch, Jacob D. (Virginia Tech, 2016-04-29)
    Multiple research projects are proposed that utilize low-level knowledge of Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design processes to enable additional research avenues. In order to accomplish these projects, Tools for Open Reconfigurable Computing (TORC) is utilized to provide a robust environment for circuit analysis and modifications. These projects rely on looking at the low-level constructs of the internals of these microchips. Through this knowledge, techniques for performing supply chain evaluations are proposed utilizing a non-binary comparison of multiple characteristic vectors between different FPGA manufacturing lots, and FPGAs that have been exposed to different environmental conditions. Second, techniques are proposed that look at design recovery by performing fuzzy segmentation and fuzzy matching algorithms to a problem area that has traditionally focused on exact graph sub-isomorphism solutions. Through these projects, additional research vectors are opened to protect and analyze the engineering efforts that are exerted in the design of FPGA and ASIC projects.
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    A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs
    Steiner, Neil Joseph (Virginia Tech, 2002-08-30)
    Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases can be used to route or trace through any device in these families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface.