VTechWorks Repository :: Browsing by Author "Wang, Shuo"

Browsing by Author "Wang, Shuo"

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The Abridgment and Relaxation Time for a Linear Multi-Scale Model Based on Multiple Site Phosphorylation
Wang, Shuo; Cao, Yang (PLOS, 2015-08-11)
Random effect in cellular systems is an important topic in systems biology and often simulated with Gillespie’s stochastic simulation algorithm (SSA). Abridgment refers to model reduction that approximates a group of reactions by a smaller group with fewer species and reactions. This paper presents a theoretical analysis, based on comparison of the first exit time, for the abridgment on a linear chain reaction model motivated by systems with multiple phosphorylation sites. The analysis shows that if the relaxation time of the fast subsystem is much smaller than the mean firing time of the slow reactions, the abridgment can be applied with little error. This analysis is further verified with numerical experiments for models of bistable switch and oscillations in which linear chain system plays a critical role.
Analysis and Application of Haseltine and Rawlings's Hybrid Stochastic Simulation Algorithm
Wang, Shuo (Virginia Tech, 2016-10-06)
Stochastic effects in cellular systems are usually modeled and simulated with Gillespie's stochastic simulation algorithm (SSA), which follows the same theoretical derivation as the chemical master equation (CME), but the low efficiency of SSA limits its application to large chemical networks. To improve efficiency of stochastic simulations, Haseltine and Rawlings proposed a hybrid of ODE and SSA algorithm, which combines ordinary differential equations (ODEs) for traditional deterministic models and SSA for stochastic models. In this dissertation, accuracy analysis, efficient implementation strategies, and application of of Haseltine and Rawlings's hybrid method (HR) to a budding yeast cell cycle model are discussed. Accuracy of the hybrid method HR is studied based on a linear chain reaction system, motivated from the modeling practice used for the budding yeast cell cycle control mechanism. Mathematical analysis and numerical results both show that the hybrid method HR is accurate if either numbers of molecules of reactants in fast reactions are above certain thresholds, or rate constants of fast reactions are much larger than rate constants of slow reactions. Our analysis also shows that the hybrid method HR allows for a much greater region in system parameter space than those for the slow scale SSA (ssSSA) and the stochastic quasi steady state assumption (SQSSA) method. Implementation of the hybrid method HR requires a stiff ODE solver for numerical integration and an efficient event-handling strategy for slow reaction firings. In this dissertation, an event-handling strategy is developed based on inverse interpolation. Performances of five wildly used stiff ODE solvers are measured in three numerical experiments. Furthermore, inspired by the strategy of the hybrid method HR, a hybrid of ODE and SSA stochastic models for the budding yeast cell cycle is developed, based on a deterministic model in the literature. Simulation results of this hybrid model match very well with biological experimental data, and this model is the first to do so with these recently available experimental data. This study demonstrates that the hybrid method HR has great potential for stochastic modeling and simulation of large biochemical networks.
Cancellation of inductor winding capacitance
(United States Patent and Trademark Office, 2009-06-30)
An inductor device or filter such as an electromagnetic interference (EMI) filter which includes an inductor provides cancellation of parasitic capacitance of the inductor and extends high frequency performance of the inductor or filter by providing the inductor using split windings and including capacitors to couple signals corresponding to those which are passed by the equivalent parallel capacitance of the inductor to another split winding or an inductor in the ground return path. Cancellation of parasitic capacitance is provided for differential mode and common mode split windings where the split windings may be either inductively coupled or not. Forming the split windings as a bifilar winding to increase coupling coefficient further improves performance and allows cancellation (as distinct from parasitic capacitance reduction) and avoidance of resonance in circuits in which an inductor is not permitted in the ground return path.
Characterization and Cancellation of High-Frequency Parasitics for EMI Filters and Noise Separators in Power Electronics Applications
Wang, Shuo (Virginia Tech, 2005-05-11)
Five chapters of this dissertation concentrate on the characterization and cancellation of high frequency parasitic parameters in EMI filters. One chapter addresses the interaction between the power interconnects and the parasitic parameters in EMI filters. The last chapter addresses the characterization, evaluation and design of noise separators. Both theoretical and experimental analyses are applied to each topic. This dissertation tries to explore several important issues related to EMI filters and noise separators. The author wishes to find some helpful approaches to benefit the understanding and design of EMI filters. The contributions of the dissertation can be summarized below: 1) Identification of mutual couplings and their effects on EMI filter performance 2) Extraction of mutual couplings using scattering parameters 3) Cancellation of mutual couplings to improve EMI filter performance 4) Cancellation of equivalent series inductance to improve capacitor performance 5) Analysis of mode transformations due to the imperfectly balanced parameters in EMI filters 6) Analysis of interaction between power interconnects and EMI filters on filter high-frequency performance 7) Modeling and design of high-performance noise separator for EMI diagnosis 8) Identification of the effects of parasitics in boost PFC inductor on DM noise Although all topics are supported by both theory and experiments, there may still be some mistakes in the dissertation. The author welcomes any advice and comments. Please send them via email to shuowang@ieee.org. Thanks
Common mode noise reduction using parasitic capacitance cancellation
(United States Patent and Trademark Office, 2009-10-13)
A negative capacitance is developed by configuring an inductor as two inversely or opposingly coupled windings having different numbers of turns and connecting a capacitance to a center tap between the two windings. The negative capacitance is developed on the side of the inductor having the winding with the greater number of turns. The negative capacitance so developed may advantageously be used to cancel any capacitance or parasitic capacitance desired for reducing power loss, increasing switching speed or reducing or eliminating common mode noise in a switched circuit such as a switched power converter
Conducted EMI Noise Prediction and Filter Design Optimization
Wang, Zijian (Virginia Tech, 2016-10-04)
Power factor correction (PFC) converter is a species of switching mode power supply (SMPS) which is widely used in offline frond-end converter for the distributed power systems to reduce the grid harmonic distortion. With the fast development of information technology and multi-media systems, high frequency PFC power supplies for servers, desktops, laptops and flat-panel TVs, etc. are required for more efficient power delivery within limited spaces. Therefore the critical conduction mode (CRM) PFC converter has been becoming more and more popular for these information technology applications due to its advantages in inherent zero-voltage soft switching (ZVS) and negligible diode reverse recovery. With the emerging of the high voltage GaN devices, the goal of achieving soft switching for high frequency PFC converters is the top priority and the trend of adopting the CRM PFC converter is becoming clearer. However, there is the stringent electromagnetic interference (EMI) regulation worldwide. For the CRM PFC converter, there are several challenges on meeting the EMI standards. First, for the CRM PFC converter, the switching frequency is variable during the half line cycle and has very wide range dependent on the AC line RMS voltage and the load, which makes it unlike the traditional constant-frequency PFC converter and therefore the knowledge and experience of the EMI characteristics for the traditional constant-frequency PFC converter cannot be directly applied to the CRM PFC converter. Second, for the CRM PFC converter, the switching frequency is also dependent on the inductance of the boost inductor. It means the EMI spectrum of the CRM PFC converter is tightly related the boost inductor selection during the design of the PFC power stage. Therefore, unlike the traditional constant-frequency PFC converter, the selection of the boost inductor is also part of the EMI filter design process and EMI filter optimization should begin at the same time when the power stage design starts. Third, since the EMI filter optimization needs to begin before the proto-type of the CRM PFC converter is completed, the traditional EMI-measurement based EMI filter design will become much more complex and time-consuming if it is applied to the CRM PFC converter. Therefore, a new methodology must be developed to evaluate the EMI performance of the CRM PFC converter, help to simplify the process of the EMI filter design and achieve the EMI filter optimization. To overcome these challenges, a novel mathematical analysis method for variable frequency PFC converter is thus proposed in this dissertation. Based on the mathematical analysis, the quasi-peak EMI noise, which is specifically required in most EMI regulation standards, is investigated and accurately predicted for the first time. A complete approximate model is derived to predict the quasi-peak DM EMI noise for the CRM PFC converter. Experiments are carried out to verify the validity of the prediction. Based on the DM EMI noise prediction, worst case analysis is carried out and the worst DM EMI noise case for all the input line and load conditions can be found to avoid the overdesign of the EMI filter. Based on the discovered worst case, criteria to ease the DM EMI filter design procedure of the CRM boost PFC are given for different boost inductor selection. Optimized design procedure of the EMI filter for the front-end converter is then discussed. Experiments are carried out to verify the validity of the whole methodology.
DM EMI Noise Analysis for Single Channel and Interleaved Boost PFC in Critical Conduction Mode
Wang, Zijian (Virginia Tech, 2010-04-30)
The critical conduction mode (CRM) power factor correction converters (PFC) are widely used in industry for low power offline switching mode power supplies. For the CRM PFC, the main advantage is to reduce turn-on loss of the main switch. However, the large inductor current ripple in CRM PFC creates huge DM EMI noise, which requires a big EMI filter. The switching frequency of the CRM PFC is variable in half line cycle which makes the EMI characteristics of the CRM PFC are not clear and have not been carefully investigated. The worst case of the EMI noise, which is the baseline to design the EMI filter, is difficult to be identified. In this paper, an approximate mathematical EMI noise model based on the investigation of the principle of the quasi-peak detection is proposed to predict the DM EMI noise of the CRM PFC. The developed prediction method is verified by measurement results and the predicted DM EMI noise is good to evaluate the EMI performance. Based on the noise prediction, the worst case analysis of the DM EMI noise in the CRM PFC is applied and the worst case can be found at some line and load condition, which will be a great help to the EMI filter design and meanwhile leave an opportunity for the optimization of the whole converter design. What is more, the worst case analysis can be extended to 2-channel interleaved CRM PFC and some interesting characteristics can be observed. For example, the great EMI performance improvement through ripple current cancellation in traditional constant frequency PFC by using interleaving techniques will not directly apply to the CRM PFC due to its variable switching frequency. More research needs to be done to abstract some design criteria for the boost inductor and EMI filter in the interleaved CRM PFC.
Electromagnetic interference noise separator
(United States Patent and Trademark Office, 2012-02-28)
Improved performance of a noise separator circuit capable of separating common mode (CM) and differential mode (DM) components of electromagnetic interference (EMI) noise are provided by arrangement of terminating impedances such that the circuit is fully symmetric with respect of a pair of input ports. The noise separator circuit is further improved by perfecting features for canceling effects of parasitic inductances and capacitances, parasitic capacitance and inductance between circuit connections such as printed circuit board traces, minimizing leakage inductance effects of pairs of coupled inductors and mutual inductance effects between pairs of coupled inductors, providing sufficient magnetizing inductance for low frequency response, and preventing saturation of inductors using switched attenuators, providing a plurality of ground planes, choices of terminating resistors and circuit layout.
EMI filter and frequency filters having capacitor with inductance cancellation loop
(United States Patent and Trademark Office, 2007-02-20)
An electromagnetic interference (EMI) filter or frequency filters (e.g. bandpass or band reject filters) in which a capacitor has an inductance cancellation loop. Inductive coupling between capacitors can allow undesired high frequencies to propagate across a filter. This is particularly a concern when the capacitors are oriented in parallel. In the present invention, the inductance cancellation loop is disposed adjacent to one capacitor so that mutual inductance between the capacitors is reduced. The attenuation of the filter at high frequencies is thereby increased. The loop can increase voltage attenuation of an EMI filter by about 20 dB. In another aspect, inductors in the filter are oriented horizontally relative to a circuitboard. Horizontal orientation reduces leakage inductance coupling between the inductors and circuitboard traces, and between the inductor and capacitors, thereby preventing unwanted propagation of high frequencies. Both measures in combination can provide a voltage attenuation increase of 30 dB.
Generalized cancellation of inductor winding capacitance
(United States Patent and Trademark Office, 2009-06-16)
An inductor device or filter such as an electromagnetic interference (EMI) filter which includes an inductor provides cancellation of parasitic capacitance of the inductor and extends high frequency performance of the inductor or filter by using an inductor network (a special case being split windings) and including capacitors to couple signals corresponding to those which are passed by the equivalent parallel capacitance of an inductor of a network of inductors such as in a multi-phase power supply of voltage converter to another inductor terminal, ground or an inductor in the ground return path. Cancellation of parasitic capacitance is provided for differential mode and common mode windings where the windings may be either inductively coupled or not. Forming the windings as a bifilar winding to increase coupling coefficient further improves performance and allows cancellation (as distinct from parasitic capacitance reduction) and avoidance of resonance in circuits in which an inductor is not permitted in the ground return path. Different inductance values and turns ratios of any or all inductors of the network, including multi-phase networks, may be accommodated.
Generalized Terminal Modeling of Electro-Magnetic Interference
Baisden, Andrew Carson (Virginia Tech, 2009-11-06)
Terminal models have been used for various power electronic applications. In this work a two- and three-terminal black box model is proposed for electro-magnetic interference (EMI) characterization. The modeling procedure starts with a time-variant system at a particular operating condition, which can be a converter, set of converters, sub-system or collection of components. A unique, linear equivalent circuit is created for applications in the frequency domain. Impedances and current / voltage sources define the noise throughout the entire EMI frequency spectrum. All parameters needed to create the model are clearly defined to ensure convergence and maximize accuracy. The model is then used to predict the attenuation caused by a filter with increased accuracy over small signal insertion gain measurements performed with network analyzers. Knowledge of EMI filters interactions with the converter allows for advanced techniques and design constraints to optimize the filter for size, weight, and cost. Additionally, the model is also demonstrated when the operating point of the system does not remain constant, as with AC power systems. Modeling of a varying operating point requires information of all the operating conditions for a complete and accurate model. However, the data collection and processing quickly become unmanageable due to the large amounts of data needed. Therefore, simplification techniques are used to reduce the complexity of the model while maintaining accuracy throughout the frequency spectrum. The modeling approach is verified for linear and power electronic networks including: a dc-dc boost converter, phase-leg module, and a simulated dc-ac inverter. The accuracy of the model is confirmed up to 100 MHz in simulation and at least 50 MHz for experimental validation.
High-Density Discrete Passive EMI Filter Design for Dc-Fed Motor Drives
Maillet, Yoann (Virginia Tech, 2008-08-29)
This works systematically presents various strategies to reduce both differential mode (DM) and common mode (CM) noise using a passive filter in a dc-fed motor drive. Following a standard approach a baseline filter is first designed to be used as reference to understand and compare the available filter topologies. Furthermore, it is used to analyze the grounding scheme of EMI filter and more specifically provide guidelines to ground single or multi stages filter. Finally, the baseline filter is investigated to recognize the possible solutions to minimize the size of the whole filter. It turns out that the CM choke and DM capacitors are the two main downsides to achieve a small EMI filter. Therefore, ideas are proposed to improve the CM choke by using other type of material such as nano crystalline core, different winding technique and new integrated method. A material comparison study is made between the common ferrite core and the nano crystalline core. Its advantages (high permeability and saturation flux density) and drawback (huge permeability drop) are analyzed thought multitudes of small and large signals tests. A novel integrated filter structure is addressed that maximizes the window area of the ferrite core and increases its leakage inductance by integrating both CM and DM inductances on the same core. Small- and large-signal experiments are conducted to verify the validity of the structure showing an effective size reduction and a good improvement at low and high frequencies. To conclude, a final filter version is proposed that reduce the volume of the baseline filter by three improve the performances in power tests.
Integrated Frequency-Selective Conduction Transmission-Line EMI Filter
Liang, Yan (Virginia Tech, 2008-12-08)
The multi-conductor lossy transmission-line model and finite element simulation tool are used to analyze the high-frequency attenuator and the DM transmission-line EMI filter. The insertion gain, transfer gain, current distribution, and input impedance of the filter under a nominal design are discussed. In order to apply the transmission-line EMI filter to power electronics systems, the performance of the filter under different dimensions, material properties, and source and load impedances must be known. The influences of twelve parameters of the DM transmission-line EMI filter on the cut-off frequency, the roll-off slope, and other characteristics of the insertion gain and transfer gain curves are investigated. The most influential parameters are identified. The current sharing between the copper and nickel conductors under different parameters are investigated. The performance of the transmission-line EMI filter under different source and load impedances is also explored. The measurement setups of the DM transmission-line EMI filter using a network analyzer have been discussed. The network analyzer has a common-ground problem that influences the measured results of the high-frequency attenuator. However, the common-ground problem has a negligible influence on the measured results of the DM transmission-line EMI filter. The connectors and copper strips between the connectors and the filter introduce parasitic inductance to the measurement setup. Both simulated and measured results show that transfer gain curve is very sensitive to the parasitic inductance. However, the insertion gain curve is not sensitive to the parasitic inductance. There are two major methods to reduce the parasitic inductance of the measurement setup: using small connectors and applying a four-terminal measurement setup. The transfer gain curves of three measurement setups are compared: the two-terminal measurement setup with BNC connectors, the two-terminal measurement setup with Sub Miniature version B (SMB) connectors, and the four-terminal measurement setup with SMB connectors. The four-terminal measurement setup with SMB connectors is the most accurate one and is applied for all the transfer gain measurements in this dissertation. This dissertation also focuses on exploring ways to improve the performance of the DM transmission-line EMI filter. Several improved structures of the DM transmission-line EMI filter are investigated. The filter structure without insulation layer can greatly reduce the thickness of the filter without changing its performance. The meander structure can increase the total length of the filter without taking up too much space and results in the cut-off frequency being shifted lower and achieving more attenuation. A prototype of the two-dielectric-layer filter structure is built and measured. The measurement result confirms that a multi-dielectric-layer structure is an effective way to achieve a lower cut-off frequency and more attenuation. This dissertation proposes a broadband DM EMI filter combining the advantages of the discrete reflective LC EMI filter and the transmission-line EMI filter. Two DM absorptive transmission-line EMI filters take the place of the two DM capacitors in the discrete reflective LC EMI filter. The measured insertion gain of the prototype has a large roll-off slope at low frequencies and large attenuation at high frequencies. The dependence of the broadband DM EMI filter on source and load impedances is also investigated. Larger load (source) impedance gives more attenuation no matter it is resistive, inductive or capacitive. The broadband DM EMI filter always has more high-frequency attenuation than the discrete reflective LC EMI filter under different load (source) impedances.
Investigation of High Performance AC/DC Front-End Converter with Digital Control for Server Applications
luo, zheng (Virginia Tech, 2008-12-05)
With the development of information technology, the market for power management of telecom and computing equipment keeps increasing. Distributed power systems are widely adopted in the telecom and computing applications for the reason of high performance and high reliability. Recently industry brought out aggressively high efficiency requirements for a wide load range for power management in telecom and computing equipment. High efficiency over a wide load range is now a requirement. On the other hand, power density is still a big challenge for front-end AC/DC converters. For DPS systems, front-end AC/DC converters are under the pressure of continuous increasing power density requirement. Although increasing switching frequency can dramatically reduce the passive component size, its effectiveness is limited by the converter efficiency and thermal management. Technologies to further increase the power density without compromising the efficiency need to be studied. The industry today is also at the beginning of transferring their design from analog control to full digital control strategy. Although issues are still exist, reducing components count, reducing the development cycle time, increasing the reliability, enhancing the circuit noise immunity and reducing the cost, all of these benefits indicate a great potential of the digital control. This thesis is focusing on how to improve the efficiency and power density by taking the advantages of the digital control. A novel Ï /2 phase shift two Channel interleaving PFC is developed to shrink the EMI filter size while maintain a good efficiency. A sophisticated power management strategy that associates with phase shedding and adaptive phase angle control is also discussed to increase the efficient for the entire load range without compromising the EMI filter size. The method of current sampling is proposed for Ï /2 phase shift two Channel interleaving PFC and multi-channel adaptive phase angle shift PFC is proposed to accurately extract the average total current information. A noise free current sampling strategy is also proposed that adjusting the sampling edge according to duty cycle information. An isolated ZVS dual boost converter is proposed to be the DC/DC stage of the front-end converter. This PWM converter has similar performance as the LLC resonant converter. It has hold up time extension capability without compromising the normal operation efficiency. It can achieve ZVS for all the switches. The current limit and SR implementation is much easier than LLC. State plane method, which potentially can be extent to other complex topologies, is used to fully study this circuit. All the operation modes are understood through the state plane method. The best operation mode is discovered for the front end applications. Light load efficiency is improved by the proposed pulse skipping method to guarantee the ZVS operation meanwhile reduce the switching frequency. Current limit operation is also proposed to restrict a best operation mode by fully taking the advantage of digital control that precisely control the circuit under the over current condition. High efficiency high power density is achieved by new topology, innovative interleaving, and the sophisticated digital control method.
Multi-phase EMI noise separator
(United States Patent and Trademark Office, 2014-04-15)
Common mode (CM) and differential mode (DM) components of multi-phase conducted electromagnetic interference (EMI) noise emanating from electronic circuits such as power converters/inverters are separated by respective coupled inductors connected to each phase of three or more phases and which are coupled to each other differently for CM and DM noise of the respective phases. The inductors of the DM separation unit are coupled such that a substantially ideal zero impedance is presented to DM noise while a high impedance is presented to CM noise. Conversely, the inductors of the CM separation unit are coupled such that a substantially ideal zero impedance is presented to CM noise while a high impedance is presented to DM noise.
PCB-Based Heterogeneous Integration of PFC/Inverter
Wang, Shuo (Virginia Tech, 2023-04-05)
State-of-the-art silicon-based power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in further improvements. Most products are custom designed with significant non-recurrent engineering and manufacturing processes that are labor intensive. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In certain cases, EMI filter design even requires a trial-and-error process. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. In a power factor correction (PFC) rectifier/inverter, the totem-pole configuration with critical conduction mode (CRM) operation to realize zero-voltage switching (ZVS) is deemed most desirable for a switching frequency 10 times higher than current practice. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, a PCB winding-based inductor has a fundamental limitation in terms of its power handling capability. The winding loss is proportional to the magnetomotive force (MMF), which is Ni. That is to say, with the number of layers (turns) and currents increased, winding loss is increased nonlinearly. Furthermore, for a large-size planar inductor, flux distribution is usually non-uniform, resulting in dramatically increased hysteresis loss and eddy loss. Thus, current designs are challenged by the capability to increase their power range. To address those issues, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes were observed in the plates. The proposed approach has a similar loss to a conventional litz wire-based design but features a higher power density and can be easily assembled in automation. A 3 kW high frequency PFC converter with 99% efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises associated with the high dv/dt of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer design. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to a point where the parasitic ringing between the inductor and its winding capacitor is observed. This dissertation presents an improved balance technique in a PCB-based coupled inductor design that compensates for the detrimental effect of the interwinding capacitors. A CM noise model is established to simplify the convoluted couplings into a decoupled representation so as to illustrate the necessary conditions for realizing a balanced network. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. The parasitic oscillation of inductors, known to be detrimental for CM noise reduction, is circumvented with the improved magnetic structure. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. This dissertation further offers an in-depth study on reducing the unwanted near-field couplings between the CM/DM inductors and DM filter capacitors, as well as unwanted self-parasitics such as the ESL of the DM capacitors. An exhaustive finite element analysis (FEA) and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects by means of physical placement of these filter components. Thus, for the first time, a single-stage EMI filter is demonstrated to meet the EMI standard in an off-line 1 kW, 12 V server power supply. With the academic contributions in this dissertation, a PCB winding-based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies.
Reducing common mode noise of power factor correction converters using general balance concept
(United States Patent and Trademark Office, 2010-09-28)
Common mode (CM) noise is substantially canceled in a switching power supply circuit such as a boost converter by providing a split inductor and analyzing the switching power supply circuit as a bridge circuit formed of the switch, portions of the split inductor and parasitic capacitances of respective portions of the power supply circuit. The bridge can then be balanced by addition of capacitance in parallel with the parasitic capacitance of a respective portion of the power supply circuit or dividing the split inductor such that a ratio of inductances of respective portions of the split inductor approximates a ratio of parasitic capacitances of the respective power supply circuit portions which may be measured or otherwise empirically determined. CM noise reduction of up to 40 db can be achieved without symmetric circuit design, addition of circuit elements or complex filtering having added cost, space requirements and power losses. Further, such a reduction in common mode noise allows simple EMI filtering arrangements to be employed further reducing cost and space requirements for the power supply circuit.
Three Dimensional Passive Integrated Electronic Ballast for Low Wattage HID Lamps
Jiang, Yan (Virginia Tech, 2009-01-27)
Around 19% of global power consumption and around 3% of global oil demand is attributable to lighting. After the first incandescent lamp was invented in 1879, more and more energy efficient lighting devices, such as gas discharge lamps, and light-emitting diodes (LED), have been developed during the last century. It is estimated that over 38% of future global lighting energy demand could be avoided by the use of more efficient lamps and ballasts [1]. High intensity discharge (HID) lamps, one category of gas discharge lamp, have been widely used in both commercial and residential lighting applications due to their merits of high efficacy, long life, compact size and good color rendition [2-4]. However, HID lamps require a well-designed ballast to stabilize the negative VI characteristics. A so-called ignitor is also needed to provide high voltage to initiate the gas discharge. Stringent input harmonic current limits, such as the IEC 61000-3-2 Class C standard, are set for lighting applications. It is well-known that high-frequency electronic ballasts can greatly save energy, improve lamp performance, and reduce the ballast size and weight compared with the conventional magnetic ballast. However, a unique phenomenon called acoustic resonance could occur in HID lamps under high-frequency operation. A low-frequency square wave current driving scheme has proved to be the only effective method to avoid acoustic resonance in HID lamps. A typical electronic HID ballast consist of three stages: power factor correction (PFC), DC/DC power regulation and low-frequency DC/AC inverter. The ignitor is usually integrated in the inverter stage. The three-stage structure results in a large size and high cost, which unfortunately offsets the merit of the HID lamp, especially in low-wattage applications. In order to make HID lamps more attractive in low-wattage and indoor applications, it is critical to reduce the size, weight and cost of HID ballasts. This dissertation is aimed at developing a compact HID with an ultra-compact ballast installed inside the lamp fixture. It is a similar concept to the compact fluorescent lamp (CFL), but it is much more challenging than the CFL. Two steps are explored to achieve high power density of the HID ballast. The first step is to improve the system structure and circuit topology. Instead of a three-stage structure, a two-stage structure is proposed, which consists of a single-stage power factor correction (SSPFC) AC/DC front-end and an unregulated DC/AC inverter/ignitor stage. An SSPFC AC/DC converter is proposed as the front-end. A DCM non-isolated flyback PFC semi-stage and a DCM buck-boost DC/DC semi-stage share the semiconductor switch, driver and PWM controller, so that the component count and cost can be reduced. The proposed SSPFC AC/DC front-end converter can achieve a high power factor, low THD, low bulk capacitor voltage, and the desired power regulation with a simple control circuit. Because the number of high-frequency switches is reduced compared to that of state-of-the-art two-stage HID ballast topologies, the switching frequency can be increased without sacrificing high efficiency, so the passive component size can be reduced. The power density of the whole ballast is increased using this two-stage structure. It results in a 2.5 times power density (6 W/in3) improvement compared to the commercial product (2.4 W/in3). The power density of the converter in discrete fashion usually suffers as a result of poor three-dimensional (3D) volume utilization due to a large component count and the different form factor of different components. In the second step, integration and packaging technologies are explored to further increase the power density. A 3D passive integrated HID ballast is proposed in this dissertation. All power passive components are designed in planar shape with a uniform form factor to fully utilize the three-dimensional space. In addition, electromagnetic integration technologies are applied to achieve structural, functional and processing integration to reduce component volume and labor cost. System partitioning, integration and packaging strategies, and implementation of major power passive integration, including an integrated EMI filter, and an integrated ignitor, will be discussed in the dissertation. The proposed integrated ballast is projected to double the power density of the discrete implementation. By installing the HID ballast inside the lamp fixture, the ambient temperature for the ballast will be much higher than the conventional separately installed ballast, and combined with a reduced size, the thermal condition for the integrated ballast will be much more severe. A thermal simulation model of the integrated ballast is built in the IDEAS simulation tool, and appropriate thermal management methods are investigated using the IDEAS simulation model. Experimental verification of various thermal management methods is provided. Based on the thermal management study, a new integrated ballast with improved thermal design is proposed.

Browsing by Author "Wang, Shuo"

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