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Browsing by Author "Wang, Yifan"

Now showing 1 - 3 of 3
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    1 kV Self-Aligned Vertical GaN Superjunction Diode
    Ma, Yunwei; Porter, Matthew; Qin, Yuan; Spencer, Joseph; Du, Zhonghao; Xiao, Ming; Wang, Yifan; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Udrea, Florin; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2024-01)
    This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance ( RON) of 0.4 mΩ⋅ cm2, and a SJ drift-region resistance ( Rdr) of 0.13 mΩ⋅ cm2. The device also exhibits good thermal stability with B V retained over 1 kV and RON dropped to 0.3 mΩ⋅ cm2 at 125oC . The trade-off between B V and Rdr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.
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    Implanted Guard Ring Edge Termination With Avalanche Capability for Vertical GaN Devices
    Wang, Yifan; Porter, M.; Xiao, M.; Lu, A.; Yee, N.; Kravchenko, I.; Srijanto, B.; Cheng, K.; Wong, H. Y.; Zhang, Y. (IEEE, 2023-10-13)
    Edge termination is the key building block in power devices to enable near-ideal, avalanche breakdown voltage (BV). This work presents the design, fabrication, and physics of a GaN guard ring (GR) edge termination formed by selective-area nitrogen implantation through an epitaxial p-GaN layer. The fabrication of this termination only includes a single implantation step that does not require precise control of implant depth, rendering a large process latitude. The selective-area implantation produces p-GaN rings that are separated by the implanted, semi-insulating regions. The number and spacing of the p-type rings are found to determine the BV of the vertical GaN p-n diode. The 16-ring structure enables a BV of 1800 V, being 88% of the theoretical 1-D parallel-plane limit. Avalanche characteristics are observed in devices with a large variety of GR designs. Finally, we present a comprehensive survey on the efficiency, fabrication complexity, real estate, and avalanche capability of various edge termination techniques that have been reported in vertical GaN devices. The high efficiency (among the highest reported in avalanche-capable GaN terminations), simple and robust fabrication process, and uniform avalanche capability make this implanted GR a promising edge termination for high-voltage GaN devices.
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    Vertical GaN diode BV maximization through rapid TCAD simulation and ML-enabled surrogate model
    Lu, Albert; Marshall, Jordan; Wang, Yifan; Xiao, Ming; Zhang, Yuhao; Wong, Hiu Yung (Pergamon-Elsevier Science, 2022-12)
    In this paper, two methodologies are used to speed up the maximization of the breakdown voltage (BV) of a vertical GaN diode that has a theoretical maximum BV of -2100 V. Firstly, we demonstrated a 5X faster accurate simulation method in Technology Computer-Aided-Design (TCAD). This allows us to find 50 % more numbers of high BV (>1400 V) designs at a given simulation time. Secondly, a machine learning (ML) model is developed using TCAD-generated data and used as a surrogate model for differential evolution optimization. It can inversely design an out-of-the-training-range structure with BV as high as 1887 V (89 % of the ideal case) compared to -1100 V designed with human domain expertise.