Browsing by Author "Zhang, Yuhao"
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- 1 kV GaN-on-Si Quasi-Vertical Schottky RectifierQin, Yuan; Xiao, Ming; Zhang, Ruizhe; Xie, Qingyun; Palacios, Tomás; Wang, Boyan; Ma, Yunwei; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Srijanto, Bernadeta R.; Zhang, Yuhao (IEEE, 2023-07)This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plane junction electric field of 2.8 MV/cm. The device also shows low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 m ·cm2. Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.
- 1 kV Self-Aligned Vertical GaN Superjunction DiodeMa, Yunwei; Porter, Matthew; Qin, Yuan; Spencer, Joseph; Du, Zhonghao; Xiao, Ming; Wang, Yifan; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Udrea, Florin; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2024-01)This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance ( RON) of 0.4 mΩ⋅ cm2, and a SJ drift-region resistance ( Rdr) of 0.13 mΩ⋅ cm2. The device also exhibits good thermal stability with B V retained over 1 kV and RON dropped to 0.3 mΩ⋅ cm2 at 125oC . The trade-off between B V and Rdr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.
- 10-kV Ga2O3 Charge-Balance Schottky Rectifier Operational at 200 ◦CQin, Yuan; Xiao, Ming; Porter, Matthew; Ma, Yunwei; Spencer, Joseph; Du, Zhonghao; Jacobs, Alan G.; Sasaki, Kohei; Wang, Han; Tadjer, Marko; Zhang, Yuhao (IEEE, 2023-08)This work demonstrates a lateral Ga2O3 Schottky barrier diode (SBD) with a breakdown voltage (BV) over 10 kV, the highest BV reported in Ga2O3 devices to date. The 10 kV SBD shows good thermal stability up to 200◦C, which is among the highest operational temperatures reported in multi-kilovolt Ga2O3 devices. The key device design for achieving such high BV is a reduced surface field (RESURF) structure based on the p-type nickel oxide (NiO), which balances the depletion charges in the n-Ga2O3 channel at high voltage. At BV, the chargebalanced Ga2O3 SBD shows an average lateral electric field (E-field) over 4.7 MV/cm at 25 ◦C and over 3.5 MV/cm at 200◦C, both of which exceed the critical E-field of GaN and SiC. The 10 kV SBD shows a specific on-resistance of 0.27 ·cm2 and a turn-on voltage of 1 V; at 200◦C, the former doubles and the latter reduces to 0.7 V. These results suggest the good potential of Ga2O3 devices for mediumand high-voltage, high-temperature power applications.
- 2 kV, 0.7 mΩ·cm2 Vertical Ga2O3 Superjunction Schottky Rectifier with Dynamic RobustnessQin, Yuan; Porter, Matthew; Xiao, Ming; Du, Zhonghao; Zhang, Hongming; Ma, Yunwei; Spencer, Joseph; Wang, Boyan; Song, Qihao; Sasaki, Kohei; Lin, Chia-Hung; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2023)We report the first experimental demonstration of a vertical superjunction device in ultra-wide bandgap (UWBG) Ga2O3. The device features 1.8 μm wide, 2×1017 cm-3 doped n-Ga2O3 pillars wrapped by the charge-balanced p-type nickel oxide (NiO). The sidewall NiO is sputtered through a novel self-align process. Benefitted from the high doping in Ga2O3, the superjunction Schottky barrier diode (SJ-SBD) achieves a ultra-low specific on-resistance (RON,SP) of 0.7 mΩ·cm2 with a low turn-on voltage of 1 V and high breakdown voltage (BV) of 2000 V. The RON,SP~BV trade-off is among the best in all WBG and UWBG power SBDs. The device also shows good thermal stability with BV > 1.8 kV at 175 oC. In the unclamped inductive switching tests, the device shows a dynamic BV of 2.2 kV and no degradation under 1.7 kV repetitive switching, verifying the fast acceptor depletion in NiO under dynamic switching. Such high-temperature and switching robustness are reported for the first time in a heterogeneous superjunction. These results show the great potential of UWBG superjunction power devices.
- Artificial Neuronal Devices Based on Emerging Materials: Neuronal Dynamics and ApplicationsLiu, Hefei; Qin, Yuan; Chen, Hung-Yu; Wu, Jiangbin; Ma, Jiahui; Du, Zhonghao; Wang, Nan; Zou, Jingyi; Lin, Sen; Zhang, Xu; Zhang, Yuhao; Wang, Han (Wiley-V C H Verlag, 2023-03)Artificial neuronal devices are critical building blocks of neuromorphic computing systems and currently the subject of intense research motivated by application needs from new computing technology and more realistic brain emulation. Researchers have proposed a range of device concepts that can mimic neuronal dynamics and functions. Although the switching physics and device structures of these artificial neurons are largely different, their behaviors can be described by several neuron models in a more unified manner. In this paper, the reports of artificial neuronal devices based on emerging volatile switching materials are reviewed from the perspective of the demonstrated neuron models, with a focus on the neuronal functions implemented in these devices and the exploitation of these functions for computational and sensing applications. Furthermore, the neuroscience inspirations and engineering methods to enrich the neuronal dynamics that remain to be implemented in artificial neuronal devices and networks toward realizing the full functionalities of biological neurons are discussed.
- Assessment of Cyber Vulnerabilities and Countermeasures for GPS-Time Synchronized Measurements in Smart GridsKhan, Imtiaj (Virginia Tech, 2024-07-02)We aim at expanding the horizon of existing research on cyberattacks against the time-syncrhonized devices such as PMUs and PDCs, along with corresponding countermeasures. We develop a PMU-PDC cybersecurity testbed at Virginia Tech Power and Energy Center (PEC) lab. The testbed is able to simulate real-world GPS-spoofing attack (GSA) and false data injection attack (FDIA) scenarios. Moreover, the testbed can incorporates cyberattack detection algorithm in pseudo real-time. After that, we propose three stealthy attack scenarios that exploit the vulnerabilities of time-synchronization for both PMU and PDC. The next part of this dissertation is the enhancement of Hankel-matrix based bad data detection model. The existing general Hankel-matrix based bad data detection model provide satisfactory performance. However, it fails in differentiating GPS-spoofing attack from FDIA. We propose an enhanced phase angle Hankel-matrix model that can conclusively identify GPS-spoofing attack. Furthermore, we reduce the computational burden for Hankel-matrix based bad data and cyberattack detection models. Finally, we verify the effectiveness of our enhanced Hankel-matrix model for proposed stealthy attack scenarios.
- A Compact Three-Phase Multi-stage EMI Filter with Compensated Parasitic-Component EffectsChen, Shin-Yu (Virginia Tech, 2023-09-14)With the advent of wide bandgap (WBG) semiconductor devices, the electromagnetic interference (EMI) emissions are more pronounced due to high slew rates in the form of high dv/dt and high di/dt at higher switching frequencies compared to the traditional silicon technology. To comply with the stringent conducted emission requirements, EMI filters are adopted to attenuate the high frequency common mode (CM) and differential mode (DM) noise through the propagation path. However, self and mutual parasitic components are known to degrade the EMI filter performance. While parasitic cancellation techniques have been discussed at length in prior literature, most of them have focused mainly on single phase applications. As such this work focuses on extending the preexisting concepts to three-phase systems. Novel component placement, winding strategy as well as shielding and grounding techniques were developed to desensitize the influence of the parasitic effects on a three-phase multi-stage filter. The effectiveness of the three-phase filter structure employing the proposed methodologies has been validated via noise measurements at the line impedance stabilization network (LISN) in a 15kW rated motor drive system. Consequently, general design guidelines have been formulated for filter topologies with different inductor and capacitor form-factors.
- Design, Fabrication, and Packaging of Gallium Oxide Schottky Barrier DiodesWang, Boyan (Virginia Tech, 2021-12-17)Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is higher than the bandgap of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this wide-bandgap is the high critical electric field of Ga2O3, which is estimated to be from 5 MV/cm to 9 MV/cm. This allows a higher Baliga’s figure of merit (BFOM), i.e., unipolar Ga2O3 devices potentially possess a smaller specific on-resistance (Ron,sp) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). This prospect makes Ga2O3 devices promising candidates for next-generation power electronics. This thesis explores the design, fabrication, and packaging of vertical Ga2O3 Schottky barrier diodes (SBDs). The power SBD allows for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. It is also a building block for many advanced power transistors. Hence, the study of Ga2O3 SBDs is expected to pave the way for developing a series of Ga2O3 power devices. In this work, a vertical β-Ga2O3 SBD with a novel edge termination, which is the small-angle beveled field plate (SABFP), is fabricated on thinned Ga2O3 substrates. This SABFP structure decreases the peak electric field (Epeak) at the triple point when the Ga2O3 SBD is reverse biased, resulting in a BV of 1.1 kV and an Epeak of 3.5 MV/cm. This device demonstrates a BFOM of 0.6 GW/cm2, which is among the highest in β-Ga2O3 power devices and is comparable to the state-of-the-art vertical GaN SBDs. The high-temperature characteristics of Ga2O3 SBDs with a 45o beveled angle sidewall edge termination are studied at temperatures up to 600 K. As compared to the state-of-the-art SiC and GaN SBDs with a similar blocking voltage, the vertical Ga2O3 SBDs are capable of operating at higher temperatures and show a smaller leakage current increase with temperature. The leakage current mechanisms were also revealed at various temperatures and reverse biases. A new fabrication method of a dielectric field plate and Ga2O3 mesa of a medium angle (10o~30o) is achieved by controlling the adhesion between the photoresist (PR) and the dielectric surface. As compared to the small-angle termination, this medium-angle edge termination can allow a superior yield and uniformity in device fabrication, at the same time maintaining the major functionalities of beveled edge termination. Good surface morphology of the field plates and Ga2O3 mesa of the medium angle 10o~30o sidewall angle is verified by atomic force microscopy. Finally, large-area Ga2O3 SBDs are fabricated and packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity and better reliability as compared to the solder joint. The metal finish on the anode and cathode has been optimized for silver sintering. Large-area, packaged Ga2O3 SBDs with an anode size of 3×3 mm2 are prototyped. They show a forward current of over 5 A, a current on/off ratio of ~109, and a BV of 190 V. To the best of the author’s knowledge, this is the first experimental demonstration of a large-area, packaged Ga2O3 power device.
- Design, Fabrication, Characterization, and Packaging of Gallium Oxide Power DiodesWang, Boyan (Virginia Tech, 2024-02-22)Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is larger than that of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this ultra-wide bandgap is the high-temperature stability due to the low intrinsic carrier concentration. Another benefit is the high critical electric field (Ec), which is estimated to be from 6 MV/cm to 8 MV/cm in Ga2O3. This allows for a superior Baliga's figure of merit (BFOM) of unipolar Ga2O3 power devices, i.e., they potentially can achieve a smaller specific on-resistance (RON,SP) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). The above prospects make Ga2O3 devices the promising candidates for next-generation power electronics. This dissertation explores the design, fabrication, characterization, and packaging of vertical β-Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes. The power SBDs allow for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. Meanwhile, the Ga2O3 power P-N diodes have the benefit of smaller leakage current, and the diode structure could be a building block for many advanced diodes and transistors. Hence, the study of Ga2O3 Schottky and P-N diodes is expected to provide the foundation for developing a series of Ga2O3 power devices. Firstly, vertical Ga2O3 Schottky and P-N diodes with a novel edge termination (ET), the multi-layer Nickel Oxide (NiO) junction termination extension (JTE), are fabricated on Ga2O3 substrates. This multi-JTE NiO structure decreases the peak electric field (Epeak) at the triple point of device edge when the Ga2O3 diodes are reversely biased. For SBDs, BV reach 2.5 kV, the 1-D junction field reaches 3.08 MV/cm, and the BFOM exceeds 1 GW/cm2. For P-N diodes, BV reaches 3.3 kV, the junction field reaches 4.2 MV/cm, and the BFOM reaches 2.6 GW/cm2. These results are among the highest in Ga2O3 power devices and are comparable to the state-of-the-art vertical GaN Schottky and P-N diodes. Notably, all these diodes are small-area devices. Secondly, large-area (3 mm×3 mm anode size) Ga2O3 Schottky and P-N diodes with high current capability are fabricated to explore the packaging, thermal management, and switching characteristics of Ga2O3 diodes. The same ET is applied for the large-area P-N diode. The fabricated large-area P-N diodes have a turn-on voltage of 2 V, a differential on-resistance (Ron) of 0.2 Ω, and they can reach at least 15 A when measured in the pulse mode. The BV of large-area Ga2O3 P-N diodes varies due to the fabrication non-uniformity, but the best device achieves a BV of 1.6 kV, standing among the highest values reported for large-area Ga2O3 diodes. Also, the large-area Ga2O3 SBDs with similar current rating but with a FP ET are fabricated mainly for the packaging and thermal management studies. Thirdly, medium-area Ga2O3 P-N diodes with a current over 1 A and a higher yield of BV are fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only ~11% of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-on/off speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes under the on-wafer switching test. These results show the viability of NiO JTE for enabling a fast switching speed in high-voltage Ga2O3 power devices. Fourthly, the fabricated large-area Ga2O3 diodes are packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity (kT) and better reliability as compared to the solder joint. Due to the low kT of Ga2O3 material, junction-side-cooled (JSC) packaging configuration is necessary for Ga2O3 devices. For the packaged device, its junction-to-case thermal resistance (RθJC) is measured in the bottom-side-cooled (BSC) and junction-side-cooled (JSC) configuration by the transient dual interface method according to the JEDEC 51-14 standard. The RθJC of the junction- and bottom-cooled Ga2O3 SBD is measured to be 0.5 K/W and 1.43 K/W, respectively. The former RθJC is lower than that of similarly-rated commercial SiC SBDs. This manifests the significance of JSC packaging for the thermal management of Ga2O3 devices. Fifthly, to evaluate the electrothermal robustness of the packaged Ga2O3 devices, the surge current capability of JSC packaged Ga2O3 SBDs are measured. The Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled (DSC) large-area Ga2O3 SBDs can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. These results show the excellent ruggedness of Ga2O3 power devices. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed and fabricated. For many power electronics applications, high current is desired; however, for emerging semiconductors, the current upscaling is difficult by directly increasing the device area because of the limitation of heat extraction capability and the limited material/processing yield. Here we explore the paralleling of multiple Ga2O3 P-N diodes to increase the current level. For each sub-module, the JSC packaging structure is used for heat extraction, and a metal post is sintered to the anode for electric field (E-field) management. RθJC is measured to be 1 W/K for each sub-module. On-board double-pulsed test is performed for both the sub-module and the full module. The sub-module and full module demonstrate 400 V, 10 A and 150 V, 70 A switching capabilities, respectively. This is the first demonstration of Ga2O3 power module and shows a promising approach to upscale of the power level of Ga2O3 power electronics. In addition to Ga2O3 device study, a research is conducted to explore the chip size (Achip) minimization for wide-bandgap (WBG) and ultra-wide bandgap (UWBG) power devices. Achip optimization is particularly critical for WBG and UWBG power devices and modules due to the high material cost. This work presents a new, holistic, electrothermal approach to optimize Achip for a given set of target specifications including BV, conduction current (I0), and switching frequency (f). The conduction and switching losses of the device are considered, as well as the heat dissipation in the chip and its package. For a given BV and I0, the optimal Achip, Wdr, and Ndr show strong dependence on f and thermal management. Our approach offers more accurate cost analysis and design guidelines for power modules. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 Schottky and P-N diodes, with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on Ga2O3 devices, including the voltage upscaling (ET), current upscaling (large-area device fabrication, packaging, and thermal management), and their concurrence (module demonstration), as well as the circuit-level switching characterizations.
- Dynamic RON Free 1.2 kV Vertical GaN JFETYang, Xin; Zhang, Ruizhe; Wang, Bixuan; Song, Qihao; Walker, Andy; Pidaparthi, Subhash; Drowley, Cliff; Zhang, Yuhao (IEEE, 2024)Dynamic on-resistance (RON) or threshold voltage (VTH) instability caused by charge trapping is one of the most crucial reliability concerns of some GaN high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic RON and VTH stability of an industrial vertical GaN transistor-NexGen’s 1200V/70mΩ fin-channel JFET, fabricated on 100 mm bulk GaN substrates. A circuit setup is deployed for the in-situ measurement of the dynamic RON under steady-state switching. The longer-term stability of RON and VTH is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no RON or VTH shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices towards power electronics applications.
- Dynamic Gate Breakdown of p-Gate GaN HEMTs in Inductive Power SwitchingWang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-02)We employ a new circuit method to characterize the gate dynamic breakdown voltage (BVdyn) of Schottky-type p-gate GaN HEMTs in power converters. Different from prior pulse I-V and DC stress tests, this method features a resonance-like gate ringing with the pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. At the increased pulse width, the gate BVdyn shows a decrease and then saturation at 21~22 V. Moreover, the gate BVdyn increases with temperature and is higher under the hard switching than that under the drain-source grounding condition. In the 400 V hard switching at 150 oC, the gate BVdyn reaches 27.5 V. Such impact of the drain switching locus and temperature on the gate BVdyn is not seen in Si and SiC power transistors tested in the same setup. These results are explained by a physics model that accounts for the electrostatics in the p-GaN gate stack in hard switching and at high temperatures. This work unveils new physics critical to the gate robustness of p-gate GaN HEMTs and manifest the necessity of the gate robustness evaluation in inductive switching conditions.
- Electro-Thermal Device-Package Co-Design for a High-Temperature Ultra-Wide-Bandgap Gallium-Oxide Power ModuleLyon, Benjamin Peter (Virginia Tech, 2023-06-22)Power electronic systems and components that can operate in environments with ambient temperatures exceeding 250 °C are needed for innovation in automotive, aerospace, and down-hole applications. With the imminent mass electrification of transportation and industry, the high-temperature electronics market value is anticipated to grow to $15 billion by the end of 2023. Conventionally, silicon (Si)-based converters are used in these applications; however, as operating temperatures continue to increase, the inherent limits of these systems are being met. The primary limitations for the high-temperature operation of semiconductor devices is the intrinsic carrier concentration, dictated primarily by the bandgap of the material, which increases with temperature. Wide-bandgap (WBG) power semiconductors, primarily silicon carbide (SiC) and gallium nitride (GaN), have been adopted for use in these applications, but exhibit a degradation in performance at elevated temperatures. As such, gallium oxide (Ga2O3), an ultrawide-bandgap (UWBG) material with controllable doping and the potential for inexpensive substrates, has presented itself as a potential contender for use in high-temperature power electronics applications. The UWBG of Ga2O3, 4.8 eV compared to 1.1 eV for Si, 3.2 eV for SiC, and 3.4 eV for GaN, allows it to achieve nearly 1033 lower intrinsic carrier concentration than Si, permitting Ga2O3 power devices to theoretically operate at significantly higher temperatures. In addition, unipolar Ga2O3 devices have a better theoretical limit with respect to the relationship between on-resistance and breakdown voltage, which could enable higher power density and power conversion efficiency. While Ga2O3 exhibits potential in these regards, its low thermal conductivity (11–27.0 W/m·K compared to 148 W/m·K for Si, 350 W/m·K for SiC, and 130 W/m·K) means that standard packaging and cooling techniques are not suitable or effective. Furthermore, conventional polymeric and organic encapsulant materials are typically limited to operating temperatures of 200 °C and novel materials must be evaluated. This work outlines and evaluates an electro-thermal device-package co-design modeling platform that can be utilized for the efficient and accurate modeling of Ga2O3 devices and their associated packaging, with the goal of overcoming the challenges of the low thermal conductivity of Ga2O3. This permits for the electrical and thermal performance of the devices and the package to be designed in tandem for an effective design. Next, six high-temperature encapsulation materials are evaluated and conclusions are drawn about each material's feasibility for use as a dielectric encapsulation material for a power module operating at temperatures exceeding 250 °C. This simulation platform and material analysis was then used to design and fabricate a 300 °C, 1.2 kV half-bridge power module utilizing Ga2O3 diodes to assess thermal and electrical performance.
- Epitaxial Gallium Oxide Heterojunctions for Vertical Power RectifiersSpencer, Joseph Andrew (Virginia Tech, 2024-06-03)At the heart of all power electronic systems lies the semiconductor, responsible for passing large amounts of current at negligible power losses in the on-state, while instantaneously switching to withstand high voltages in the off-state. For decades silicon (Si) has dominated nearly all aspects of electronic systems including power. As importunity for efficiency at higher power and fast switching speeds grows, the environments with which these systems are being tasked to operate in has also increased in rigor. This has placed semiconductors at the forefront of innovation as novel materials are being explored in hopes of meeting the demands for the future of power electronics. This exploration of novel materials for power electronics has come to fruition as the performance limits of narrow bandgap (EG) materials such as Si (1.1 eV) have been reached. The EG is a key measure of a materials ability to operate at high voltages and within high temperature environments. This is due to the direct relationship of the EG to the critical field strength which enables increased performance beyond that of narrow band gap materials such as Si and gallium arsenide. Wide bandgap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN) with EG 3.3 eV and 3.4 eV, respectively, have emerged within the power electronics field to offer increased breakdown voltages (VBR) at lower on-resistances. However, ultrawide bandgap (UWBG) devices possess greater potential with superior performance limits in comparison to SiC and GaN. Ga2O3 (4.8 eV) is the only UWBG semiconductor with melt-growth capabilities that has already demonstrated research grade wafers up to 6" in diameter. Ga2O3 is also advantaged by the ability to grow thick, lowly-doped homoepitaxial drift regions from methods such as halide vapor phase epitaxy (HVPE) and metal organic chemical vapor deposition (MOCVD). This makes Ga2O3 a prime candidate for vertical power rectifiers as thick, high quality drift regions are a necessity for high voltage devices such as the PN diode, junction barrier Schottky (JBS) diode, merged-PiN-Schottky (MPS) diode, and Schottky barrier diode (SBD). However, Ga2O3 exhibits a lack of p-type conductive that arises from an absence of dispersion within the valence band maximum. This has caused researchers to abandon the idea of homojunction devices that Si, SiC, and GaN devices benefit from; shifting to a heterojunction approach where NiO (3.7 eV) provides the source of p-type conductivity. This complicates fabrication and device characterization particularly for the Ga2O3 JBS diode where an etched Ga2O3-NiO heterojunction has thus far been unreported throughout the literature. This work investigates the numerous individual aspects that comprise an etched Ga2O3 heterojunction device which include the etching method, post etch damage removal and its impact on electrical performance, and ohmic and Schottky contacts critical for a JBS diode; all culminating in the demonstration of a JBS and MPS diodes. We also report our investigations into co-doping of Ga2O3 that yield degenerately doped epitaxial layers with record mobility (μ) values. While not directly correlated with Ga2O3-NiO heterojunction devices, this study lays the ground work for semi-insulating Ga2O3 depletion into unintentionally doped (UID) n-type Ga2O3.
- Gate Lifetime of P-Gate GaN HEMT in Inductive Power SwitchingWang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-06)The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage (VG) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under VG overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like VG overshoots with pulse width down to 20 ns and dVG/dt up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency (fSW). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of VG overshoot (VG(PK)) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max VG(PK) for 10-year gate lifetime is predicted under different fSW in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT’s converter applications and a new method for the device gate qualification.
- Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit MethodWang, Bixuan; Zhang, Ruizhe; Song, Qihao; Wang, Hengyu; He, Quanbo; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2024-01)The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the DC bias stress or pulse I-V method, neither of which resembles the gate voltage (VGS) overshoot waveform in practical converters. This work develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like VGS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BVDYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive VGS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the VGS peak value and little dependence on the switching frequency. More interestingly, the gate's BVDYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 oC and 100 kHz, the VGS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.
- Hard Switched Robustness of Wide Bandgap Power Semiconductor DevicesKozak, Joseph Peter (Virginia Tech, 2021-08-30)As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors.
- High-Efficiency and High-Frequency Resonant Converter Based Single-Stage Soft-Switching Isolated Inverter Design and Optimization with Gallium-Nitride (GaN)Wen, Hao (Virginia Tech, 2021-09-30)Isolated inverter can provide galvanic isolation which is necessary for some applications with safety regulations. Traditionally, a two-stage configuration is widely applied with isolated dc-dc stage and a sinusoidal pulse-width-modulated (SPWM) dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Meanwhile, a large dc bus capacitor is needed to attenuate the double line frequency from SPWM for two-stage configuration. Therefore, the single-stage approach including an isolated dc-rectified sine stage and a line frequency unfolder is preferable. Since the unfolder circuit is at line frequency being almost lossless, the isolated dc-rectified sine stage becomes critical. However, the relevant research for the single-stage isolated inverter is limited. People either utilize PWM based converter as dc-rectified sine stage with duty cycle adjustment or apply SRC or LLC resonant converter for better soft switching characteristics. For PWM based converter, hard switching restricts the overall inverter efficiency, while for SRC/LLC, enough wide voltage gain range and full range ZVS are the major issues. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. This dissertation will first propose the optimization methods for LLC converter dc-dc conversion. ZVS models are derived to ensure fully ZVS performance for primary side GaN devices. As a large part in loss breakdown, the optimization for transformer is essential. The LLC converter can achieve above 99% efficiency with proposed optimization approach. Moreover, the channel turn-off energy model is presented for a more accurate loss analysis. With all the design and optimization considerations, a MHz LLC converter based isolated inverter is designed and a hybrid modulation method is proposed, which includes full bridge (FB) VFM for output high line region and half bridge (HB) VFM for output low line region. By changing from FB to HB, the output voltage gain is reduced to half to have a wider voltage gain range. However, the total harmonic distortion (THD) of output voltage at light load will be impacted since the voltage gain will be higher with lighter load at the maximum switching frequency. A MHz LCLCL converter based isolated inverter is proposed for a better output voltage THD at light load conditions. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point at their resonant frequency, which shows superior performance for rectified sine wave generation. Besides the better THD performance, the LCLCL converter based isolated inverter also features for easier control, better ZVS performance and narrower switching frequency range. Meanwhile, the LCLCL based inverter topology has bi-directional power flow capability as well. With variable frequency modulation for ac-dc, this topology is still a single-stage solution compared to the traditional two-stage solution including PFC + LLC configuration.
- Investigation of Multiphase Coupled Inductor Topologies for Point-of-Load ApplicationsZhu, Feiyang (Virginia Tech, 2023-07-18)As a scalable, high-efficiency, and simple converter topology, an interleaved, multiphase buck converter has been widely used to power microprocessors in information industry. As modern microprocessors continuously advance, the required current for high-performance microprocessors used in data center applications could be several hundreds of amperes with a current slew rate larger than 1000 A/μs. This poses great challenges for a high-efficiency, high-power-density voltage regulator design with a fast transient response. On the other hand, the design challenges of voltage regulators in mobile applications are also increasing due to the stringent requirement on the device thickness and the battery life. In a multiphase buck converter, discrete inductors are widely used as energy storage elements. However, this solution has a limited transient response with a large size of magnetic components. To overcome these issues, coupled inductor is proposed to realize a small steady-state current ripple, a fast transient response, and a small inductor size at the same time. Although lots of studies have been conducted in the topic of the coupled inductor, there are still several challenges unsolved in this area. These challenges are addressed through a comprehensive study in this dissertation. First, a comprehensive analysis of different coupled inductor structures is crucial to identify the benefits and limitations of each inductor structure and provide design guidance under different application requirements. Based on the coupling mechanism, different coupled inductor structures are categorized as a direct-coupled inductor (DCL), an indirect-coupled inductor (ICL) or a hybrid-coupled inductor (HCL) in this work. The performance of these three types of coupled inductors is analyzed in detail through the equivalent inductance analysis and the magnetic flux analysis. For the applications that require a small phase number, a DCL can achieve the smallest inductor size with a given inductance requirement. As the phase number increases, it is beneficial to use an ICL and an HCL due to their symmetrical, simple, and scalable inductor structures. As compared to an ICL, an HCL can achieve a smaller inductor size due to the flux-cancellation effect. The difference between a DCL, an ICL and an HCL are revealed quantitively with several design examples through this study. Second, the steady-state inductance (Lss) and the transient inductance (Ltr) are two key design parameters for coupled inductors. A large Lss and a small Ltr are preferred from the circuit performance point of view. However, there is a design conflict in an ICL and an HCL under the inductor size constraint, where reducing Ltr also results in a smaller Lss. A variable coupling coefficient concept is proposed to overcome this issue. With the same Lss, the proposed method can achieve a smaller Ltr during load transients as compared with the conventional method. This concept is realized by applying a nonlinear inductor in the additional winding loop with the current in this loop as the control source. Compared with the conventional structure, the proposed structure can achieve a great output voltage spike reduction and output capacitance reduction. Third, although an ICL and an HCL are promising candidates for multiphase coupled inductors, an extra inductor is required in the additional winding loop to adjust the coupling coefficient. This additional inductor occupies extra space. To shrink the total inductor size, several improved magnetic core structures are proposed to achieve the controllable coupling through the magnetic integration for an ICL and an HCL. Furthermore, the thickness of the core plate can be significantly reduced by the improved core structure for an HCL. Overall, it is demonstrated that the inductor footprint is greatly reduced by the proposed core structure, as compared with the conventional solution. Lastly, a novel PCB-embedded coupled inductor structure is proposed for a 20MHz integrated voltage regulator (IVR) for mobile applications. To achieve a small inductor footprint and a low profile, the inductor structure with a lateral flux pattern and direct coupling is adopted. Compared with the state-of-the-art solution, the proposed structure can adjust the coupling in a simple core structure by changing the inductor winding pattern. The proposed structure integrates multiple inductors into one magnetic core and is embedded into PCB with a total thickness of 0.54 mm. In contrast to prior arts, the proposed inductor structure features a large inductance density and quality factor with a much smaller DC resistance (DCR), thus is seen as a promising candidate for IVR applications.
- Junction Based Gallium Nitride Power DevicesMa, Yunwei (Virginia Tech, 2023-09-05)Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices.
- Multidimensional device architectures for efficient power electronicsZhang, Yuhao; Udrea, Florin; Wang, Han (Springer Nature, 2022-11-17)Power semiconductor devices are key to delivering high-efficiency energy conversion in power electronics systems, which is critical in efforts to reduce energy loss, cut carbon dioxide emissions and create more sustainable technology. Although the use of wide or ultrawide-bandgap materials will be required to develop improved power devices, multidimensional architectures can also improve performance, regardless of the underlying material technology. In particular, multidimensional device architectures—such as superjunction, multi-channel and multi-gate technologies—can enable advances in the speed, efficiency and form factor of power electronics systems. Here we review the development of multidimensional device architectures for efficient power electronics. We explore the rationale for using multidimensional architectures and the different architectures available. We also consider the performance limits, scaling and material figure of merits of the architectures, and identify key technological challenges that need to be addressed to realize the full potential of the approach.