A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware

Abstract

A new design methodology that produces hardware

solutions for performing real-time image processing is

presented here. This design methodology provides

significant advantages over traditional hardware

design approaches by translating real-time image

processing tasks into the gate-level resources of

programmable logic-based hardware architectures.

The use of programmable logic allows

high-performance solutions to be realized with very

efficient utilization of available logic and

interconnection resources. These implementations

provide comparable performance at a lower cost

than other available programmable logic-based

hardware architectures. This new design

methodology is based on two components: a

programmable logic-based destination hardware

architecture and a suite of development system

software. The destination hardware architecture is a

Custom Computing Machine (CCM) that contains

multiple Field Programmable Gate Array (FPGA)

chips. FPGA chips provide gate-level

programmability for the hardware architecture.

Sophisticated software development tools, called the

TRAVERSE development system software, are

created to overcome the significant amount of time

and expertise required to manually utilize this

gate-level programmability. The new hardware

architecture and development system software

combine to establish a unique design methodology.

There are several distinct contributions provided by

this dissertation. The new flexible MORRPH

hardware architecture provides a more efficient

solution for creating real-time image processing

computing machines than current commercial

hardware architectures. The TRAVERSE

development system software is the first integrated

development system specifically for creating real-time

image processing designs with multiple FPGA-based

CCMs. New standards and design conventions are

defined specifically for creating solutions to low-level

image processing tasks, using the MORRPH

architecture for verification. The circuit partitioning

and global routing programs of the TRAVERSE

development system software enable automated

translation of image processing designs into the

resources of multiple FPGA chips in the hardware

architecture. In a broad sense, the individual

contributions of this dissertation combine to create a

new design methodology that will change the way

hardware solutions are created for real-time image

processing in the future.