Design of Integrated, Low Power, Radio Receivers in BiCMOS Technologies

Abstract

Despite increasing levels of integration in modern electronic products, radio receiver designs continue to rely on discrete LC, ceramic, and electro-acoustic devices for the realization of RF and IF bandpass filtering. Although considerable research has been directed at developing suitable switched-capacitor and Gm-C based replacements for these filters, the resulting designs have yet to see substantial commercial application. A critical problem faced by existing active filter implementations is found to be the power consumption required to simultaneously achieve narrow fractional bandwidths and acceptable dynamic range. This power consumption, which can reach several hundred milliwatts, is incompatible with portable wireless product design. Additional problems include the complexity of tuning control circuits required to achieve small fractional bandwidths, and diffculties in extending filter designs to higher frequencies. These problems are examined in depth, and performace bounds and new implementation techniques are considered. A detailed study of active filters reveals that their dynamic range limitations are fundamentally the result of regenerative gain associated with the realization of high-Q poles. Thus, some form of energy storage and exchange mechanism is shown to be required to decrease the regeneration needed. This leads to an investigation of on-chip LC filtering. Itis shown that on-chip spiral inductors can be designed to resonate with both intentional and parasitic capacitances, forming stable tuned circuits operating from 100 MHz to over 1 GHz. Although the Q of the inductors employed is typically small (Q < 10), negative resistance circuits can be used to increase the effective Q to arbitrarily high values. Hence, very small fractional bandwidths (< 2%) can be obtained. Moreover, even a small inductor Q is shown to provide significant increases in dynamic range over that achievable in fully active filter designs. Important practical considerations surrounding the implementation of Q-enhanced LC filters in silicon CMOS processes are then investigated, including realizing the necessary on-chip spiral inductors and Q-enhancement circuits, predicting frequency and Q tolerances and temperature stability, and developing real-time frequency and Q tuning mechanisms. These issues are studied in depth and two prototype filters designed to validate theoretical predictions are reported. Performance levels achieved by these prototypes indicate that Q-enhanced filtering offers a viable approach to solving the on-chip bandpass filtering problem. These filters can therefore be expected to play an important role in the development of future integrated receiver products.