An Effort toward Building more Secure and Efficient Physical Unclonable Functions
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Over the last decade, there has been a tremendous growth in the number of electronic devices and applications. One of the very important aspects to deal with such proliferation of ICs is their security. Establishing the Identity (ID) of a device is the cornerstone of any secure application. Typically, the IDs of devices are stored in non-volatile memories (NVM) or through burning fuses on ICs. However, through such traditional techniques, IDs are vulnerable to attacks. Further, maintaining such secrets in NVMs is expensive. Physical Unclonable Functions (PUF) provide an alternative method for creating chip IDs. They exploit the uncontrollable variations that exist in IC manufacturing to generate identifiers. However, since PUFs exploit the small mismatch across identically designed circuits, the responses of PUFs are prone to error in the presence of unwanted variations in the operating temperature, supply voltage, and other noises. The overarching goal of this work is to develop silicon PUFs that are highly efficient and stable to such noises. In addition, to make PUFs more attractive for low cost and tiny embedded systems, our goal is to develop PUFs with minimal area and power consumption for a given ID length and security requirement. Techniques to develop such PUFs span different abstraction levels ranging from technology-independent application-level techniques to technology-dependent device-level ones. In this dissertation, we present different technology-independent and technology-dependent techniques and evaluate which techniques are good candidates for improving different qualities of PUFs. In technology-independent techniques, we propose two modifications to a conventional PUF architecture, which are detailed in this thesis. Both modifications result in a PUF that is more efficient in terms of area and power. Compared to the traditional architecture, for a given silicon real estate, the proposed architecture provides over two orders of magnitude larger $C/R$ space and it has higher resistance toward modeling attacks. Under technology-dependent methods, we investigate multiple techniques that improve stability and efficiency of PUF designs. In one approach, we propose a novel PUF design with a similar architecture to that of a traditional design, where we replace large and power hungry digital components with more efficient analog components. In another technique, we exploit the differences between pMOS and nMOS transistors in their variation of threshold voltage (Vth) and in the temperature coefficients of Vth to significantly improve the stability of bi-stable PUFs. We also use circuit-level simulations to evaluate the stability of silicon PUFs to aging degradation. We believe that our technology-independent techniques are good candidates for improving overall efficiency of PUFs in terms of both operation and implementation costs, suitable for PUFs with tight constraints on cost for design and test. However, with regards to improving the stability of PUFs, it is cost-effective to use our technology-dependent techniques as long as the extra effort for implementation and testing can be tolerated.
- Doctoral Dissertations