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dc.contributor.authorMiao, Zichenen_US
dc.description.abstractSilicon carbide (SiC) outperform Si chips in terms of high blocking voltage capability, low on-resistance, high-temperature operation, and high switching frequency. Several SiC MOSFETs are usually paralleled to increase current capability, considering cost effectiveness and manufacturability. For a SiC power module with current rating higher than 100 A, high did/dt and dvds/dt could possibly cause cross-turn-on (crosstalk-induced turn-on) through the gate-to-drain capacitance Cgd of the MOSFET dies and the package inductances. Mismatches in threshold voltage (Vth) up to 33% have been observed among paralleled SiC MOSFETs. This leads to unbalanced transient peak currents and switching energies. Both cross-turn-on and current unbalance degrade the reliability of a power module. Increasing the immunity to cross-turn-on while maintaining the similar switching energies and balancing the transient peak currents below 10% without sacrificing the voltage stress are the goals of this work. Development of a SPICE model free of non-convergence – A simulation model for a SiC power module is necessary for evaluations of cross-turn-on and current unbalance; however, most SiC power modules do not have models. No existing modeling methods discuss how to build an accurate SPICE model that is free of non-convergence when hundreds of parasitic inductances are present. A modeling process is introduced for paralleled MOSFETs encapsulated in a power module that gives access to both the internal channel current and voltage of each bare die inside the package. This model is free of non-convergence and accurate. Parasitic ac resistances, dc resistances, and ac inductances are extracted by Q3D Extractor. Non-convergence is avoided by including the ac resistance of the conduction trace in the model. Also, a series model which is set default in Q3D Extractor is converted to parallel model to accurately reflect how the current flows through the dc and ac resistances of the trace. A complete SPICE model of a commercial SiC power module was derived and validated by experiments. The error between predicted turn-on peak current of the developed model and that of the experimental data is 2%, significantly lower than the 28% difference between prediction result of commercial model and experimental data. Detection of internal cross-turn-on – Terminal current of a power module does not reflect the internal channel current due to the numerous parasitic inductances of the package. No existing method is able to detect the cross-turn-on in a power module since dies are usually encapsulated and the channel currents are hard to measure. A nonintrusive method to identify cross-turn-on based on the changing ringing current is developed. The detection method was analyzed theoretically and validated by experiments using a 1.2-kV SiC module. The negative drive voltage and gate resistance for safe operation can be determined by the detection method. Influence of layout symmetry on immunity to cross-turn-on – Gate resistance, gate-to-drain capacitance of the MOSFET, slew rate of drain-to-source voltage, and temperature have been recognized as the only elements impacting the immunity to cross-turn-on for a single chip and module. Layout symmetry is newly discovered to be another factor that contributes to the immunity. Asymmetrical and symmetrical modules following commercial layouts were tested by a double pulse tester. The peak cross-turn-on currents, high-side switching energy, and total switching energy at various input voltages, low-side gate resistances, and load currents are normalized for comparison. The peak cross-turn-on current of the symmetrical module is 84% lower than that of the asymmetrical module at nominal condition. Longer power-loop and gate-drive loop are required to achieve symmetrical layout for more than two dies in parallel. This increases the low-side switching energy of the symmetrical module. The total switching energies of the two modules are similar. In this case, a symmetrical layout is still recommended since current stress caused by cross-turn-on is much smaller in symmetrical module than in the asymmetrical module and chances to have shoot-through between the high side and the low side are reduced. Magnetic integration into a power module for current balancing – Existing power modules do not have balanced transient currents when threshold voltage mismatch exists. A module with integrated coupled inductors was designed, fabricated, and validated to be effective to balance the currents without sacrificing voltage stress and switching energy. The designed integrated coupled inductors achieve inverse coupling by utilizing the copper trace of the substrate and bond wires and have the following features: size comparable to the silicon carbide (SiC) die, coupling coefficient higher than 0.98, tens of nH operating at tens of MHz, and current rating of tens of Amperes. The coupled inductors with the magnetic material of low-temperature co-fired ceramics (LTCC) are compatible with existing packaging technology for module fabrication. The effectiveness of reducing transient-current mismatch at various input voltages, load currents, and gate resistances was verified by experiments. Compared with the baseline module following commercial practice, the module with integrated coupled inductors reduces current unbalance from 36% to 6.4% and turn-on-energy difference from 28% to 2.6% while maintaining the same total switching energy and a negligible change of voltage stress.en_US
dc.publisherVirginia Techen_US
dc.rightsThis item is protected by copyright and/or related rights. Some uses of this item may be deemed fair and permitted by law even without permission from the rights holder(s), or the rights holder(s) may have licensed the work for use under certain conditions. For other uses you need to obtain permission from the rights holder(s).en_US
dc.subjectmagnetic integrationen_US
dc.subjectparalleled SiC MOSFETsen_US
dc.subjectcurrent balancingen_US
dc.titlePackaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETsen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.contributor.committeechairNgo, Khai D. T.en_US
dc.contributor.committeememberSouthward, Steve C.en_US
dc.contributor.committeememberLu, Guo Quanen_US
dc.contributor.committeememberManteghi, Majiden_US
dc.contributor.committeememberBurgos, Rolandoen_US

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