Enabling Energy-Efficient Hybrid CMOS and Embedded Memory Accelerators for Neuromorphic Computing at the Edge

Abstract

The deployment of deep learning at the edge promises advances in autonomous driving, computer vision, and IoT, but is limited by the inefficiencies of conventional von Neumann architectures. The physical separation of memory and processing creates a performance bottleneck, with high energy and latency costs. This dissertation investigates hybrid CMOS–memristor accelerators that leverage non von Neumann paradigms to address these constraints. The first contribution explores computing-in-memory (CIM) architectures using memristors, which combine storage and computation to reduce data movement. While memristors offer density, low power, and nonvolatility, challenges such as resistance variation degrade inference accuracy. To mitigate this, novel two-layer memristor structures with improved thermal properties are proposed to enhance reliability. The second focus is on integrating spiking neural networks (SNNs) with memristor crossbars. By mimicking biological spike-based communication, SNNs improve robustness and energy efficiency. New encoding schemes and Leaky Integrate-and-Fire (LIF) neuron models are developed to optimize temporal information processing. We then explore reservoir computing (RC) architecture to reduce the training complexity of deep models on ASICs. By training only the output layer while preserving spatiotemporal dynamics in the reservoir, RC reduces hardware cost and time while maintaining performance. The proposed architectures are evaluated on edge applications, including autonomous driving and image recognition, where energy efficiency, adaptability, and reliability are critical. Results show that these reconfigurable accelerators improve accuracy and robustness while meeting strict power and area constraints, advancing the design of scalable edge AI hardware.