Samhita: Virtual Shared Memory for Non-Cache-Coherent Systems
| dc.contributor.author | Ramesh, Bharath | en |
| dc.contributor.committeechair | Varadarajan, Srinidhi | en |
| dc.contributor.committeechair | Ribbens, Calvin J. | en |
| dc.contributor.committeemember | Jones, Mark T. | en |
| dc.contributor.committeemember | Ramakrishnan, Naren | en |
| dc.contributor.committeemember | Kafura, Dennis G. | en |
| dc.contributor.department | Computer Science | en |
| dc.date.accessioned | 2013-08-06T08:00:20Z | en |
| dc.date.available | 2013-08-06T08:00:20Z | en |
| dc.date.issued | 2013-08-05 | en |
| dc.description.abstract | Among the key challenges of computing today are the emergence of many-core architectures and the resulting need to effectively exploit explicit parallelism. Indeed, programmers are striving to exploit parallelism across virtually all platforms and application domains. The shared memory programming model effectively addresses the parallelism needs of mainstream computing (e.g., portable devices, laptops, desktop, servers), giving rise to a growing ecosystem of shared memory parallel techniques, tools, and design practices. However, to meet the extreme demands for processing and memory of critical problem domains, including scientific computation and data intensive computing, computing researchers continue to innovate in the high-end distributed memory architecture space to create cost-effective and scalable solutions. The emerging distributed memory architectures are both highly parallel and increasingly heterogeneous. As a result, they do not present the programmer with a cache-coherent view of shared memory, either across the entire system or even at the level of an individual node. Furthermore, it remains an open research question which programming model is best for the heterogeneous platforms that feature multiple traditional processors along with accelerators or co-processors. Hence, we have two contradicting trends. On the one hand, programming convenience and the presence of shared memory call for a shared memory programming model across the entire heterogeneous system. On the other hand, increasingly parallel and heterogeneous nodes lacking cache-coherent shared memory call for a message passing model. In this dissertation, we present the architecture of Samhita, a distributed shared memory (DSM) system that addresses the challenge of providing shared memory for non-cache-coherent systems. We define regional consistency (RegC), the memory consistency model implemented by Samhita. We present performance results for Samhita on several computational kernels and benchmarks, on both cluster supercomputers and heterogeneous systems. The results demonstrate the promising potential of Samhita and the RegC model, and include the largest scale evaluation by a significant margin for any DSM system reported to date. | en |
| dc.description.degree | Ph. D. | en |
| dc.format.medium | ETD | en |
| dc.identifier.other | vt_gsexam:1413 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/23687 | en |
| dc.publisher | Virginia Tech | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject | Distributed Shared Memory | en |
| dc.subject | Virtual Shared Memory | en |
| dc.subject | Memory Consistency | en |
| dc.title | Samhita: Virtual Shared Memory for Non-Cache-Coherent Systems | en |
| dc.type | Dissertation | en |
| thesis.degree.discipline | Computer Science and Applications | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | doctoral | en |
| thesis.degree.name | Ph. D. | en |
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