Automatic Generation of Efficient Parallel Streaming Structures for Hardware Implementation
dc.contributor.author | Koehn, Thaddeus E. | en |
dc.contributor.committeechair | Athanas, Peter M. | en |
dc.contributor.committeemember | Ernst, Joseph M. | en |
dc.contributor.committeemember | Dietrich, Carl B. | en |
dc.contributor.committeemember | Buehrer, R. Michael | en |
dc.contributor.committeemember | McGwier, Robert W. | en |
dc.contributor.department | Electrical and ComputerEngineering | en |
dc.date.accessioned | 2018-05-25T06:00:20Z | en |
dc.date.available | 2018-05-25T06:00:20Z | en |
dc.date.issued | 2016-11-30 | en |
dc.description.abstract | Digital signal processing systems demand higher computational performance and more operations per second than ever before, and this trend is not expected to end any time soon. Processing architectures must adapt in order to meet these demands. The two techniques most prevalent for achieving throughput constraints are parallel processing and stream processing. By combining these techniques, significant throughput improvements have been achieved. These preliminary results apply to specific applications, and general tools for automation are in their infancy. In this dissertation techniques are developed to automatically generate efficient parallel streaming hardware architectures. | en |
dc.description.abstractgeneral | The algorithms that process data have been getting more complicated requiring more operations in less time. This trend has been going on for many years with no end in sight. Techniques must be developed to allow the processing system to meet these requirements. Assembly line techniques, or stream processing allows multiple stages in which each stage is working on a different piece of data. Increasing the number of assembly lines can further increase the number of operations, but results in large overheads. This dissertation develops automation techniques to reduce these overheads resulting in efficient hardware. | en |
dc.description.degree | Ph. D. | en |
dc.format.medium | ETD | en |
dc.identifier.other | vt_gsexam:9096 | en |
dc.identifier.uri | http://hdl.handle.net/10919/83391 | en |
dc.publisher | Virginia Tech | en |
dc.rights | In Copyright | en |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
dc.subject | Streaming | en |
dc.subject | Field programmable gate arrays | en |
dc.subject | Hardware | en |
dc.subject | Digital Signal Processing | en |
dc.subject | Permutation | en |
dc.title | Automatic Generation of Efficient Parallel Streaming Structures for Hardware Implementation | en |
dc.type | Dissertation | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
thesis.degree.level | doctoral | en |
thesis.degree.name | Ph. D. | en |
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