Adaptive bus voltage positioning for two-stage voltage regulators

Alteration of voltage input to a voltage regulator output stage from a V_bus regulator stage in a two-stage voltage regulator provides optimal V_bus voltage placement for a wide range of current loads to increase voltage regulator efficiency and is particularly suited to CPUs having power-saving sleep modes of operation. An optimal voltage is selected or developed in response to information concerning operational mode or current consumption of the powered device. As a perfecting feature of one embodiment of the invention in which a discrete V_bus voltage is selected based on operational mode, the selected voltage is adjusted to further optimize the matching of the V_bus voltage placement to the load and provides a continuous range of voltages. In a second embodiment the entire V_bus positioning function is performed in response to current load information. A feed-forward arrangement is provided to avoid transient spikes as the V_bus voltage placement is altered.