An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits

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dc.contributor.authorLee, Hyung K.en
dc.contributor.authorHa, Dong S.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2017-09-18T10:11:48Zen
dc.date.available2017-09-18T10:11:48Zen
dc.date.issued1994-01-01en
dc.date.updated2017-09-18T10:11:47Zen
dc.description.abstractIn this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, calledSOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into anequivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives testpatterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set sizeare introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANOachieves high SOP fault coverage and short processing time.en
dc.description.versionPublished versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationHyung K. Lee and Dong S. Ha, “An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits,” VLSI Design, vol. 2, no. 3, pp. 199-207, 1994. doi:10.1155/1994/71941en
dc.identifier.doihttps://doi.org/10.1155/1994/71941en
dc.identifier.urihttp://hdl.handle.net/10919/79118en
dc.language.isoenen
dc.publisherHindawien
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.holderCopyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.en
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.titleAn Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuitsen
dc.title.serialVLSI Designen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten

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