Robustness and Stability of Gallium Nitride Transistors in Dynamic Power Switching

Wide-bandgap gallium nitride (GaN) high electron mobility transistors (HEMTs) are gaining increased adoption in applications like mobile electronics and data centers. Benefitting from the high channel mobility and the high breakdown field of GaN, GaN power HEMTs enable low specific on-resistance and small capacitance and thus become attractive for high-frequency applications. In addition, most commercial GaN power HEMTs are fabricated on Si substrates up to 8 inches, allowing for a remarkable cost advantage. However, a by-product of the low-cost GaN-on-Si wafer (and conductive Si substrate) is the high voltage drop and high electric field (E-field) in the GaN buffer layers and transition layers sandwiched between the GaN channel and Si substrate. To boost the vertical blocking capability and minimize the leakage current, the GaN buffer layer is usually doped with carbon or iron, which can introduce complex carrier traps. This can further lead to the dynamic shifts of various parameters in GaN-on-Si HEMTs, which can cause their stability and robustness issues in practical circuit operations.
This dissertation work studies the robustness and stability of GaN power HEMTs in dynamic power switching. The structures of most GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness and stability. Simple equipment-level static characterization may not reflect the real device characteristics in circuit-level operation. Based on the relevance between the stress condition and the device's safe operating area (SOA), this dissertation is divided into two parts. In each part, two representative GaN power devices, the standalone GaN HEMT, and the GaN-Si cascode HEMT, are studied. The dissertation's first half discusses the GaN HEMT behavior outside of SOA, with a focus on the robustness of GaN HEMTs in overvoltage power switching. This focus is motivated by the lack of avalanche capability of GaN HEMTs, which is a unique device physics distinct from SiC/Si power transistors. Instead of withstanding the surge energy through avalanching, GaN HEMTs rely on their high breakdown voltage margin to withstand the surge energy, which can trigger new degradation and failure mechanisms. Therefore, investigating the GaN HEMTs' robustness in overvoltage switching is of great interest. The robustness study begins with a standalone depletion-mode (D-mode) MIS (Metal-Insulator-Semiconductor) HEMT in an overvoltage hard-switching. The device is found to show a decreased threshold voltage and increased saturation current after stress. These parametric shifts increase as switching cycles increase but reach a saturation point before one million cycles. The root cause is believed to be the impact-ionization-generated holes trapped underneath the insulated gate. This is verified by the physics-based TCAD (Technology Computer-Aided Design) simulation. After the stress, MIS-HEMT cannot fully recover naturally. Applying at positive gate-to-source bias (VGS) is found to be able to accelerate the threshold voltage recovery but not the saturation current recovery, while a 50-V substrate bias is shown to fully recover both parameters. These findings provide new insight into the hole trapping/de-trapping dynamics and the benefits of substrate voltage control in GaN MIS-HEMTs. Then, a cascode GaN HEMT, which contains a D-mode GaN MIS-HEMT and an enhancement-mode (E-mode) Si MOSFET, is studied similarly in overvoltage stress produced by an inductive switching circuit. Parametric shifts are found in cascode GaN HEMTs, including the unstable breakdown voltage and increased on-resistance. The crosstalk between Si MOSFET and GaN HEMT is believed to account for these parametric shifts. A decapsulated device is developed based on the commercial part to monitor the Si MOSFET behavior. Si MOSFET is found to avalanche during the overvoltage switching. The parametric shifts are believed to be due to the avalanche-generated electrons, which are injected into the GaN HEMTs and trapped in the GaN buffer layer. These electron traps alter the E-field distribution of the GaN HEMT and induce parametric shifts. The second half of the dissertation focuses on the GaN HEMT's stability inside the SOA, with a focus on the non-ideal power loss generated in high-frequency switching. The output capacitance (COSS) loss has recently been found to be the dominant loss in soft switching, which is the loss associated with GaN HEMT's COSS when it is charged and discharged. This process should be lossless for an ideal capacitor, but GaN HEMT experiences a hysteresis COSS loss during each charging-discharging cycle due to the COSS instability in dynamic power switching. The COSS loss study starts with an accurate and easy-to-implement test platform, which is proven to have good robustness and repeatability. The measured COSS loss of different types of GaN HEMTs is modeled, followed by the investigation of the COSS loss origin. TCAD simulation reveals the fundamental role of trappings in the cause of COSS loss in standalone GaN HEMTs. For the cascode GaN HEMT, two additional loss mechanisms are involved as compared to the standalone GaN HEMTs: Si avalanche energy loss and GaN early turn-on loss. This makes cascode GaN HEMT experiences much higher COSS loss than standalone GaN HEMTs. The COSS loss of cascode GaN HEMT is quantitively analyzed, and a mitigation strategy is proposed for suppressing the COSS loss of cascode GaN HEMTs. Then, a circuit-level method is proposed to reduce the COSS loss of standalone GaN HEMT by dynamically tuning the substrate bias, which is verified with a standalone D-mode GaN HEMT. The Si substrate bias can follow the drain voltage in a certain ratio by tuning the capacitance ratio between the drain, substrate, and source. It is found that with a substrate bias of 1/4 to 1/2 of the drain voltage, the COSS loss can be reduced by 86%. This result removes a critical roadblock for deploying GaN HEMTs in high-frequency, soft-switching applications. Finally, the COSS loss of similarly rated Si and SiC power transistors is characterized using the developed test platform. The capability of the setup is further broadened to testing power diodes. Some similarities and distinctions are found in the COSS loss behavior between GaN HEMTs and Si/SiC devices. Also, an EDISS validation process is provided for the UIS-based method in an operating class-E converter, verifying the effectiveness and accuracy of the proposed method. This provides important references for selecting the optimal power devices for high-frequency applications.