A Modular Flow for Rapid FPGA Design Implementation

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dc.contributor.authorLove, Andrew R.en
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.committeememberDietrich, Carl B.en
dc.contributor.committeememberNazhandali, Leylaen
dc.contributor.committeememberFeng, Wu-chunen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2015-03-11T08:00:08Zen
dc.date.available2015-03-11T08:00:08Zen
dc.date.issued2015-03-10en
dc.description.abstractThis dissertation proposes an alternative FPGA design compilation flow to reduce the back-end time required to implement an FPGA design to below the level at which the user's attention is lost. To do so, this flow focuses on enforcing modular design for both productivity and code reuse, while minimizing reliance on standard tools. This can be achieved by using a library of precompiled modules and associated meta-data to enable bitstream-level assembly of desired designs. In so doing, assembly would occur in a fraction of the time of traditional back-end tools. Modules could be bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. This turbo flow (TFlow) aims to enable software-like turn-around time for faster prototyping by leveraging precompiled components. As a result, large device compilations would be assembled in seconds, within the deadline imposed by the human attention span.en
dc.description.degreePh. D.en
dc.format.mediumETDen
dc.identifier.othervt_gsexam:4634en
dc.identifier.urihttp://hdl.handle.net/10919/51608en
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFPGA Productivityen
dc.subjectModular Designen
dc.subjectInstant Gratificationen
dc.subjectAttention Spanen
dc.subjectDesign Assembly Flowen
dc.titleA Modular Flow for Rapid FPGA Design Implementationen
dc.typeDissertationen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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