Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits

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dc.contributor.authorLee, Hyung Kien
dc.contributor.committeechairHa, D.S.en
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberMidkiff, Scott F.en
dc.contributor.committeememberShaffer, Clifford A.en
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:14:36Zen
dc.date.adate2008-06-06en
dc.date.available2014-03-14T21:14:36Zen
dc.date.issued1993-12-05en
dc.date.rdate2008-06-06en
dc.date.sdate2008-06-06en
dc.description.abstractIn this dissertation, we propose two fault simulators, called HOPE and HOPE2, and an autolllatic test pattern generator (ATPG), called ATHENA, for synchronous and asynchronous sequential circuits. HOPE is a parallel fault simulator for synchronous sequential circuits. In HOPE, a packet of 32 faults is simulated in parallel. Several new heuristics are employed in HOPE to accelerate the parallel fault simulation. The heuristics are 1) a reduction of faults to be simulated in parallel, 2) a new fault injection method called functional fault injection, and J) a combination of static and dynamic fault ordering methods. According to our experiments, HOPE is about 2.2 times, on the average, faster than a competing fault simulator, called PROOFS (1]--[2]. for 16 ISCAS89 benchmark circuits [3]. HOPE2 and ATHENA are a fault simulator and an A TPG for asynchronous sequential circuits, respectively. The key idea employed in HOPE2 and ATHENA is 10 transform an asynchronous sequential circuit into a synchronous sequential circuit through remodeling memory elements. We proposed various modeling techniques which transform any asynchronous sequential circuit into a synChronous sequential circuit. Once an asyncllfonous circuit is transformed into a synchronous circuit, various techniques developed for synchronous sequential circuits are employed in HOPE2 and ATHENA. HOPE2 employs the parallel simulation techniques of HOPE. ATHENA employs the back algorithm [4] for test generation, and the parallel fault simulation teChnique for fault simulation. HOPE2 and ATHENA can manage industrial circuits consisting of latches, flip-flops with set/reset, tristate gates, BUS elements, bi-directional I/O pins, mutiplexers, ROMs and RAMs. OUf experimental results on various industrial circuits show that HOPE2 is about two times faster than a commercial fault simulator, the Verifault fault simulator of Cadence, while requiring much smaller memory size. ATHENA also shows high performance for various industrial circuits.en
dc.description.degreePh. D.en
dc.format.extentxii, 195 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-06062008-171759en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06062008-171759/en
dc.identifier.urihttp://hdl.handle.net/10919/38494en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V856_1993.L444.pdfen
dc.relation.isformatofOCLC# 30805385en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V856 1993.L444en
dc.subject.lcshElectric fault location -- Computer simulationen
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Testingen
dc.titleFault simulation and test pattern generation for synchronous and asynchronous sequential circuitsen
dc.typeDissertationen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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