Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits
dc.contributor.author | Lee, Hyung Ki | en |
dc.contributor.committeechair | Ha, D.S. | en |
dc.contributor.committeemember | Armstrong, James R. | en |
dc.contributor.committeemember | Midkiff, Scott F. | en |
dc.contributor.committeemember | Shaffer, Clifford A. | en |
dc.contributor.committeemember | Tront, Joseph G. | en |
dc.contributor.department | Electrical Engineering | en |
dc.date.accessioned | 2014-03-14T21:14:36Z | en |
dc.date.adate | 2008-06-06 | en |
dc.date.available | 2014-03-14T21:14:36Z | en |
dc.date.issued | 1993-12-05 | en |
dc.date.rdate | 2008-06-06 | en |
dc.date.sdate | 2008-06-06 | en |
dc.description.abstract | In this dissertation, we propose two fault simulators, called HOPE and HOPE2, and an autolllatic test pattern generator (ATPG), called ATHENA, for synchronous and asynchronous sequential circuits. HOPE is a parallel fault simulator for synchronous sequential circuits. In HOPE, a packet of 32 faults is simulated in parallel. Several new heuristics are employed in HOPE to accelerate the parallel fault simulation. The heuristics are 1) a reduction of faults to be simulated in parallel, 2) a new fault injection method called functional fault injection, and J) a combination of static and dynamic fault ordering methods. According to our experiments, HOPE is about 2.2 times, on the average, faster than a competing fault simulator, called PROOFS (1]--[2]. for 16 ISCAS89 benchmark circuits [3]. HOPE2 and ATHENA are a fault simulator and an A TPG for asynchronous sequential circuits, respectively. The key idea employed in HOPE2 and ATHENA is 10 transform an asynchronous sequential circuit into a synchronous sequential circuit through remodeling memory elements. We proposed various modeling techniques which transform any asynchronous sequential circuit into a synChronous sequential circuit. Once an asyncllfonous circuit is transformed into a synchronous circuit, various techniques developed for synchronous sequential circuits are employed in HOPE2 and ATHENA. HOPE2 employs the parallel simulation techniques of HOPE. ATHENA employs the back algorithm [4] for test generation, and the parallel fault simulation teChnique for fault simulation. HOPE2 and ATHENA can manage industrial circuits consisting of latches, flip-flops with set/reset, tristate gates, BUS elements, bi-directional I/O pins, mutiplexers, ROMs and RAMs. OUf experimental results on various industrial circuits show that HOPE2 is about two times faster than a commercial fault simulator, the Verifault fault simulator of Cadence, while requiring much smaller memory size. ATHENA also shows high performance for various industrial circuits. | en |
dc.description.degree | Ph. D. | en |
dc.format.extent | xii, 195 leaves | en |
dc.format.medium | BTD | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.other | etd-06062008-171759 | en |
dc.identifier.sourceurl | http://scholar.lib.vt.edu/theses/available/etd-06062008-171759/ | en |
dc.identifier.uri | http://hdl.handle.net/10919/38494 | en |
dc.language.iso | en | en |
dc.publisher | Virginia Tech | en |
dc.relation.haspart | LD5655.V856_1993.L444.pdf | en |
dc.relation.isformatof | OCLC# 30805385 | en |
dc.rights | In Copyright | en |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
dc.subject.lcc | LD5655.V856 1993.L444 | en |
dc.subject.lcsh | Electric fault location -- Computer simulation | en |
dc.subject.lcsh | Integrated circuits -- Very large scale integration -- Testing | en |
dc.title | Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits | en |
dc.type | Dissertation | en |
dc.type.dcmitype | Text | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
thesis.degree.level | doctoral | en |
thesis.degree.name | Ph. D. | en |
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