dc.contributor.author	Kim, Han Bin	en
dc.contributor.committeechair	Ha, Dong Sam	en
dc.contributor.committeemember	Armstrong, James R.	en
dc.contributor.committeemember	Gray, Festus Gail	en
dc.contributor.committeemember	Midkiff, Scott F.	en
dc.contributor.committeemember	Henry, Sallie M.	en
dc.contributor.department	Electrical and Computer Engineering	en
dc.date.accessioned	2014-03-14T20:21:09Z	en
dc.date.adate	1999-12-31	en
dc.date.available	2014-03-14T20:21:09Z	en
dc.date.issued	1999-12-15	en
dc.date.rdate	2000-12-31	en
dc.date.sdate	1999-12-23	en
dc.description.abstract	A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a local optimum. In this thesis, we present three methods, which aim to address the problem. The first method tries to find a register assignment for each k-test session in a heuristic manner, where k=1,2,…,N and N is the number of modules of the circuit. Therefore, it offers a range of designs with different figures of merit in area and test time. The second method is based on integer linear programming (ILP). The proposed ILP based method performs the three tasks, assignments of registers, interconnections, and BIST registers, concurrently to yield optimal or near-optimal designs. We describe a complete set of ILP formulations for the three tasks. The ILP based method achieves optimal solutions for most circuits in hardware overhead, but it takes long processing time. The third method, the region-wise heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time. To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis method, we implemented a DSP circuit; an 8x8 two-dimensional discrete cosine transform (DCT) processor. We implemented two versions of the algorithm, one with incorporation of our BIST method and the other without BIST, to verify the validity of our simplified cost model to estimate BIST area overhead. The two major parts of the circuit, data path and controller, were synthesized using our high-level BIST synthesis tool. All the circuits are implemented and laid out using an ASIC design flow developed at Virginia Tech. Experimental results show that the three proposed high-level BIST synthesis methods perform better than or comparable to existing BIST synthesis systems. They indeed yield various designs that enable users to trade between area overhead and test time. The region-wise heuristic method reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised compared with the ILP-based optimal method. The implementation of DCT circuits demonstrate that our method is applicable to industry size circuits, and the BIST area overhead measured at the layout is close to the estimated one.	en
dc.description.degree	Ph. D.	en
dc.identifier.other	etd-122399-220228	en
dc.identifier.sourceurl	http://scholar.lib.vt.edu/theses/available/etd-122399-220228/	en
dc.identifier.uri	http://hdl.handle.net/10919/30257	en
dc.publisher	Virginia Tech	en
dc.relation.haspart	ch5exp~1.pdf	en
dc.relation.haspart	ch4dct.pdf	en
dc.relation.haspart	ch3pro~1.pdf	en
dc.relation.haspart	ch2bac~1.pdf	en
dc.relation.haspart	abslis~1.pdf	en
dc.rights	In Copyright	en
dc.rights.uri	http://rightsstatements.org/vocab/InC/1.0/	en
dc.subject	ASIC	en
dc.subject	DSP	en
dc.subject	Built-In Self-Test	en
dc.subject	BIST	en
dc.subject	High-Level Synthesis	en
dc.subject	Data Path	en
dc.title	High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit	en
dc.type	Dissertation	en
thesis.degree.discipline	Electrical and Computer Engineering	en
thesis.degree.grantor	Virginia Polytechnic Institute and State University	en
thesis.degree.level	doctoral	en
thesis.degree.name	Ph. D.	en

High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit

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