Enhanced Gate-Driver Techniques and SiC-based Power-cell Design and Assessment for Medium-Voltage Applications

Due to the limitations of silicon (Si), there is a paradigm shift in research focusing on wide-bandgap-based (WBG) materials. SiC power semiconductors exhibit superiority in terms of switching speed, higher breakdown electric field, and high working temperature, slowly becoming a global solution in harsh medium-voltage (MV) high-power environments. However, to utilize the SiC MOSFET device to achieve those next-generation, high-density, high-efficiency power electronics converters, one must solve a plethora of challenges.

For the MV SiC MOSFET device, a high-performance gate-driver (GD) is a key component required to maximize the beneficial SiC MOSFET characteristics. GD units must overcome associated challenges of electro-magnetic interference (EMI) with regards to common-mode (CM) currents and cross-talk, low driving loop inductance required for fast switching, and device short-circuit (SC) protection. Developed GDs (for 1.2 kV, and 10 kV devices) are able to sustain dv/dt higher than 100 V/ns, have less than 5 nH gate loop inductance, and SC protection, turning off the device within 1.5 us.

Even with the introduction of SiC MOSFETs, power devices remain the most reliability-critical component in the converter, due to large junction temperature (Tj) fluctuations causing accelerated wear-out. Real-time (online) measurement of the Tj can help improve long-term reliability by enabling active thermal control, monitoring, and prognostics. An online Tj estimation is accomplished by generating integrated intelligence on the GD level. The developed Tj sensor exhibits a maximum error less than 5 degrees Celsius, having excellent repeatability of 1.2 degrees Celsius. Additionally, degradation monitoring and an aging compensation scheme are discussed, in order to maintain the accuracy of the sensor throughout the device's lifetime.

Since ultra high-voltage SiC MOSFET devices (20 kV) are impractical, the modular multilevel converter (MMC) emerged as a prospective topology to achieve MV power conversion. If the kernal part of the power-cell (main constitutive part of the MMC converter) is an SiC MOSFET, the design is able to achieve very high-density and high-efficiency. To ensure a successful operation of the power-cell, a systematic design and assessment methodology (DAM) is explored, based on the 10 kV SiC MOSFET power-cell. It simultaneously addresses challenges of high-voltage insulation, high dv/dt and EMI, component and system protections, as well as thermal management. The developed power-cell achieved high-power density of 11.9 kW/l, with measured peak efficiency of n=99.3 %@10 kHz. It successfully operated at Vdc=6 kV, I=84 A, fsw>5 kHz, Tj<150 degrees Celsius and had high switching speeds over 100 V/ns.

Lastly, to achieve high-power density and high-efficiency on the MV converter level, challenges of high-voltage insulation, high-bandwidth control, EMI, and thermal management must be solved. Novel switching cycle control (SCC) and integrated capacitor blocked-transistor (ICBT) control methodologies were developed, overcoming the drawbacks of conventional MMC control. These novel types of control enable extreme reduction in passive component size, increase the efficiency, and can operate in dc/dc, dc/ac, mode, potentially opening the modular converter to applications in which it was not previously used. In order to explore the aforementioned benefits, a modular, scalable, 2-cell per arm, prototype MV converter based on the developed power-cell is constructed. The converter successfully operated at Vdc=12 kV, I=28 A, fsw=10 kHz, with high switching speeds, exhibiting high transient immunity in both SCC and ICBT.