A formal model for behavioral test generation

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dc.contributor.authorCho, Chang H.en
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberBrown, Ezra A.en
dc.contributor.committeememberHa, Dong Samen
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:14:11Zen
dc.date.adate2008-06-06en
dc.date.available2014-03-14T21:14:11Zen
dc.date.issued1994-02-08en
dc.date.rdate2008-06-06en
dc.date.sdate2008-06-06en
dc.description.abstractA formal behavioral test generation algorithm, called the B-algorithm, is presented together with a behavioral VHDL model and a realistic behavioral fault model. Using the behavioral VHDL model, a behavioral VHDL circuit description is represented as a set of equivalent process Statements and connections among them. The behavioral fault model consists of three types of behavioral faults (behavioral stuck-at faults, behavioral stuck-open faults, and micro-operation faults) which well represent faulty behaviors of a digital circuit. The behavioral VHDL model and the behavioral fault model improve the efficiency of test generation by reducing the size of the domain searched during the test generation procedure. The B-algorithm generates tests directly from behavioral VHDL circuit descriptions using three basic test generation operations (activation, propagation, and justification), which are systematically executed by manipulating three data structures (B-frontier, J-frontier, and A-queue). Rules for the test generation operations are formally defined using the concepts of two-phase activation and two-phase propagation. The difference between simulation semantics and test generation semantics is discussed, and a method of efficiently assigning time periods without being affected by simulation semantics is proposed. A method of handling bus resolution functions, reconvergent fanout, and feedback loops during test generation is discussed. Two-phase testing, a testing strategy where a fault is detected using two consecutive test sequences, is introduced and 1s formally incorporated into the B-algorithm.en
dc.description.degreePh. D.en
dc.format.extentviii, 164 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-06062008-170406en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06062008-170406/en
dc.identifier.urihttp://hdl.handle.net/10919/38405en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V856_1994.C56.pdfen
dc.relation.isformatofOCLC# 30828762en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V856 1994.C56en
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Testingen
dc.titleA formal model for behavioral test generationen
dc.typeDissertationen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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