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FPGA Dynamic Power Minimization through Placement and Routing Constraints

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dc.contributor.authorWang, Lien
dc.contributor.authorFrench, Matthewen
dc.contributor.authorDavoodi, Azadehen
dc.contributor.authorAgarwal, Deepaken
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2012-08-24T12:16:23Zen
dc.date.available2012-08-24T12:16:23Zen
dc.date.issued2006-08-29en
dc.date.updated2012-08-24T12:16:23Zen
dc.description.abstractField-programmable gate arrays (FPGAs) are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR) tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE) is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.en
dc.description.versionPublished versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationEURASIP Journal on Embedded Systems. 2006 Aug 29;2006(1):031605en
dc.identifier.doihttps://doi.org/10.1155/ES/2006/31605en
dc.identifier.urihttp://hdl.handle.net/10919/18949en
dc.language.isoenen
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.holderLi Wang et al.; licensee BioMed Central Ltd.en
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.titleFPGA Dynamic Power Minimization through Placement and Routing Constraintsen
dc.title.serialEURASIP Journal on Embedded Systemsen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten

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