Space Vector Techniques for a Binary-Cascaded Multilevel Inverter Operating Under Reduced Common-Mode Voltage With Reduced Commutations

dc.contributor.authorGutierrez, Bryanen
dc.contributor.authorBaek, Seunghoonen
dc.contributor.authorLai, Jih-Shengen
dc.date.accessioned2023-03-27T13:34:30Zen
dc.date.available2023-03-27T13:34:30Zen
dc.date.issued2022-10en
dc.date.updated2023-03-25T05:07:22Zen
dc.description.abstractThis article presents a novel space vector pulsewidth modulation (SVPWM) for a three-phase binary-cascaded multilevel inverter (BCMLI). The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. The gh coordinate system can ease the digital implementation, but to generate the inverter's abc states from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This article proposes a further reduction of computations by directly generating the abc state with minimum common-mode voltage (CMV) from a gh vector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the BCMLI and further applied to any M-level MLI. Also, if M is considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with the line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experimental results of a BCMLI are presented to verify the effectiveness of the proposed technique.en
dc.description.versionPublished versionen
dc.format.extentPages 615-627en
dc.format.mimetypeapplication/pdfen
dc.identifier.doihttps://doi.org/10.1109/OJIES.2022.3214150en
dc.identifier.eissn2644-1284en
dc.identifier.issn2644-1284en
dc.identifier.orcidLai, Jih [0000-0003-2315-8460]en
dc.identifier.urihttp://hdl.handle.net/10919/114181en
dc.identifier.volume3en
dc.language.isoenen
dc.publisherIEEEen
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subjectCommon-mode voltageen
dc.titleSpace Vector Techniques for a Binary-Cascaded Multilevel Inverter Operating Under Reduced Common-Mode Voltage With Reduced Commutationsen
dc.title.serialIEEE Open Journal of the Industrial Electronics Societyen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten
dc.type.otherJournal Articleen
pubs.organisational-group/Virginia Techen
pubs.organisational-group/Virginia Tech/Engineeringen
pubs.organisational-group/Virginia Tech/Engineering/Electrical and Computer Engineeringen
pubs.organisational-group/Virginia Tech/All T&R Facultyen
pubs.organisational-group/Virginia Tech/Engineering/COE T&R Facultyen

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