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Extending and Programming the NVMe I/O Determinism Interface for Flash Arrays

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dc.contributor.authorLi, Huaichengen
dc.contributor.authorPutra, Martinen
dc.contributor.authorShi, Ronalden
dc.contributor.authorKurnia, Fadhilen
dc.contributor.authorLin, Xingen
dc.contributor.authorDo, Jaeyoungen
dc.contributor.authorKistijantoro, Achmaden
dc.contributor.authorGanger, Gregoryen
dc.contributor.authorGunawi, Haryadien
dc.date.accessioned2023-03-01T13:32:13Zen
dc.date.available2023-03-01T13:32:13Zen
dc.date.issued2023-01-11en
dc.date.updated2023-03-01T01:40:50Zen
dc.description.abstractPredictable latency on flash storage is a long-pursuit goal, yet unpredictability stays due to the unavoidable disturbance from many well-known SSD internal activities. To combat this issue, the recent NVMe IO Determinism (IOD) interface advocates host-level controls to SSD internal management tasks. Although promising, challenges remain on how to exploit it for truly predictable performance. We present IODA,1 an I/O deterministic flash array design built on top of small but powerful extensions to the IOD interface for easy deployment. IODA exploits data redundancy in the context of IOD for a strong latency predictability contract. In IODA, SSDs are expected to quickly fail an I/O on purpose to allow predictable I/Os through proactive data reconstruction. In the case of concurrent internal operations, IODA introduces busy remaining time exposure and predictable-latency-window formulation to guarantee predictable data reconstructions. Overall, IODA only adds five new fields to the NVMe interface and a small modification in the flash firmware while keeping most of the complexity in the host OS. Our evaluation shows that IODA improves the 95–99.99th latencies by up to 75×. IODA is also the nearest to the ideal, no disturbance case compared to seven state-of-the-art preemption, suspension, GC coordination, partitioning, tiny-tail flash controller, prediction, and proactive approaches.en
dc.description.versionPublished versionen
dc.format.extentPages 1-33en
dc.format.mimetypeapplication/pdfen
dc.identifier.doihttps://doi.org/10.1145/3568427en
dc.identifier.eissn1553-3093en
dc.identifier.issn1553-3077en
dc.identifier.issue1en
dc.identifier.orcidLi, Huaicheng [0000-0002-3155-0203]en
dc.identifier.urihttp://hdl.handle.net/10919/114012en
dc.identifier.volume19en
dc.language.isoenen
dc.publisherACMen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectSoftware/hardware co-designen
dc.subjectpredictable latencyen
dc.subjectSSDen
dc.titleExtending and Programming the NVMe I/O Determinism Interface for Flash Arraysen
dc.title.serialACM Transactions on Storageen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten
dc.type.otherArticleen
pubs.organisational-group/Virginia Techen
pubs.organisational-group/Virginia Tech/Engineeringen
pubs.organisational-group/Virginia Tech/Engineering/Computer Scienceen
pubs.organisational-group/Virginia Tech/All T&R Facultyen
pubs.organisational-group/Virginia Tech/Engineering/COE T&R Facultyen

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