Hierarchical test generation for CMOS circuits

dc.contributor.authorBollinger, S. Wayneen
dc.contributor.committeechairMidkiff, Scott F.en
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.committeememberKafura, Dennis G.en
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:16:30Zen
dc.date.adate2008-07-28en
dc.date.available2014-03-14T21:16:30Zen
dc.date.issued1992-03-05en
dc.date.rdate2008-07-28en
dc.date.sdate2008-07-28en
dc.description.abstractAs advances in very large scale integration (VLSI) technology lead to higher levels of circuit integration and new design styles and fabrication processes, traditional test generation techniques fail to adequately address the problems of how to (l) accurately represent the structure of design styles and physical faults, and (2) manage the high computational costs and memory resource requirements caused by the complexity of VLSI. This research investigates a modular, hierarchical approach to test generation for combinational complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design techniques are used in the development of a hierarchical test generation application implemented using C++. In doing this, the primary objectives were to produce a easily maintainable system, provide an extensible framework for test generation supporting the straightforward incorporation of new types of circuit primitives and faults, and retain the same level of computational efficiency that can be achieved using a procedural language such as C. Characteristics of the object-oriented hierarchical test generation application, such as expandability and run-time efficiency, are compared to those of a standard gate-level test generation program implemented using C and a procedural design approach.en
dc.description.degreePh. D.en
dc.format.extentxii, 168 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-07282008-134708en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07282008-134708/en
dc.identifier.urihttp://hdl.handle.net/10919/38899en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V856_1992.B644.pdfen
dc.relation.isformatofOCLC# 26091172en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V856 1992.B644en
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Testingen
dc.subject.lcshMetal oxide semiconductors, Complementary -- Testingen
dc.titleHierarchical test generation for CMOS circuitsen
dc.typeDissertationen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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