CMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/s

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dc.contributor.authorChong, Josephen
dc.contributor.committeechairHa, Dong Samen
dc.contributor.committeememberWang, Anboen
dc.contributor.committeememberLester, Luke F.en
dc.contributor.committeememberYi, Yangen
dc.contributor.committeememberChoi, Seongim Sarahen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2018-06-22T08:00:49Zen
dc.date.available2018-06-22T08:00:49Zen
dc.date.issued2018-06-21en
dc.description.abstractCircuits to extend operation data-rate of a optical receiver is investigated in the dissertation. A new input-stage topology for a transimpedance amplifier (TIA) is designed to achieve 50% higher data-rate is presented, and a new architecture for clock recovery is proposed for 50% higher clock rate. The TIA is based on a gm-boosted common-gate amplifier. The input-resistance is reduced by modifying a transistor at input stage to be diode-connected, and therefore lowers R-C time constant at the input and yielding higher input pole frequency. It also allows removal of input inductor, which reduces design complexity. The proposed circuit was designed and fabricated in 32 nm CMOS SOI technology. Compared to TIAs which mostly operates at 50 GHz bandwidth or lower, the presented TIA stage achieves bandwidth of 74 GHz and gain of 37 dBohms while dissipating 16.5 mW under 1.5V supply voltage. For the clock recovery circuit, a phase-locked loop is designed consisting of a frequency doubling mechanism, a mixer-based phase detector and a 40 GHz voltage-controlled oscillator. The proposed frequency doubling mechanism is an all-analog architecture instead of the conventional digital XOR gate approach. This approach realizes clock-rate of 40 GHz, which is at least 50% higher than other circuits with mixer-based phase detector. Implemented with 0.13-μm CMOS technology, the clock recovery circuit presents peak-to-peak clock jitter of 2.38 ps while consuming 112 mW from a 1.8 V supply.en
dc.description.degreePh. D.en
dc.format.mediumETDen
dc.identifier.othervt_gsexam:16229en
dc.identifier.urihttp://hdl.handle.net/10919/83608en
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectAnalog Integrated Circuiten
dc.subjectCMOSen
dc.subjectOptical Communicationen
dc.subjectTransimpedance Amplifieren
dc.subjectClock and Data Recoveryen
dc.titleCMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/sen
dc.typeDissertationen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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