Concurrent detection of transient faults in microprocessors
| dc.contributor.author | Khan, Mohammad Ziaullah | en |
| dc.contributor.committeechair | Tront, Joseph G. | en |
| dc.contributor.committeemember | Armstrong, James R. | en |
| dc.contributor.committeemember | Ha, Dong S. | en |
| dc.contributor.committeemember | Brown, Ezra A. | en |
| dc.contributor.committeemember | Nunnally, Charles E. | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2015-07-09T20:43:18Z | en |
| dc.date.available | 2015-07-09T20:43:18Z | en |
| dc.date.issued | 1989 | en |
| dc.description.abstract | A large number of errors in digital systems are due to the presence of transient faults. This is especially true of microprocessor-based systems working in a radiation environment that experience transient faults due to single event upsets. These upsets cause a temporary change in the state of the system without any permanent damage. Because of their random and non-recurring nature, transient faults are difficult to detect and isolate, hence they become a source of major concern, especially in critical real-time application areas. Concurrent detection of these errors is necessary for real-time operation. Most existing fault tolerance schemes either use redundancy to mask effects of transient faults or monitor the system for abnormal operations and then perform recovery operation. Although very effective, redundancy schemes incur substantial overhead that makes them unsuitable for small systems. Most monitoring schemes, on the other hand, only detect control flow errors. A new approach called Concurrent Processor Monitoring for on-line detection of transient faults is proposed that attempts to achieve high error coverage with small error detection latency. The concept of the execution profile of an instruction is defined and is used for detecting control flow and execution errors. To implement this scheme, a watchdog processor is designed for monitoring operation of the main processor. The effectiveness of this technique is demonstrated through computer simulations. | en |
| dc.description.degree | Ph. D. | en |
| dc.format.extent | xii, 191 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/54212 | en |
| dc.language.iso | en_US | en |
| dc.publisher | Virginia Polytechnic Institute and State University | en |
| dc.relation.isformatof | OCLC# 20137598 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V856 1989.K526 | en |
| dc.subject.lcsh | Fault location (Engineering) | en |
| dc.subject.lcsh | Fault-tolerant computing | en |
| dc.title | Concurrent detection of transient faults in microprocessors | en |
| dc.type | Dissertation | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | doctoral | en |
| thesis.degree.name | Ph. D. | en |
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