Technology for Planar Power Semiconductor Devices Package with Improved Voltage Rating

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dc.contributor.authorXu, Jingen
dc.contributor.committeechairNgo, Khai D. T.en
dc.contributor.committeememberLiu, Yiluen
dc.contributor.committeememberNelson, Douglas J.en
dc.contributor.committeememberLu, Guo-Quanen
dc.contributor.committeemembervan Wyk, Jacobus Danielen
dc.contributor.committeememberOdendaal, Willem Gerhardusen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:08:01Zen
dc.date.adate2009-03-24en
dc.date.available2014-03-14T20:08:01Zen
dc.date.issued2008-12-05en
dc.date.rdate2009-03-24en
dc.date.sdate2009-03-06en
dc.description.abstractThe high-voltage SiC power semiconductor devices have been developed in recent years. They cause an urgent in the need for the power semiconductor packaging to have not only low interconnect resistance, less noise, less parasitic oscillations, improved reliability, and better thermal management, but also High-Voltage (HV) blocking capability. The existing power semiconductor packaging technologies includes wire-bonding interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI), power overlay (POL) technology, and embedded power (EP) technology. None of them meets the requirements of low profile and high voltage rating. The objective of the work in this dissertation is to propose and design a high-voltage power semiconductor device packaging method with low electric field stress and low profile to meet the requirments of high-voltage blocking capability. The main contributions of the work presented in this dissertation are: 1. Understanding the electric field distribution in the package. The power semiconductor packaging is simulated by using Finite Element Analysis (FEA) software. The electric field distribution is known and the locations of high electric field concentration are identified. 2. Development of planar high-voltage power semiconductor device packaging method With the proposed structure in the dissertation, the electric field distribution of a planar device package is improved and the high electric field intensity is relieved. 3. Development of design guidelines for the propsed planar high-voltage device packaging method. The influence of the structure dimensions and the material properties is studied. An optimal design is identified. The design guideline is given. 4. Fabrication and experimental verification of the proposed high-voltage device packaging method A detailed fabrication procedure which follows the design guideline is presented. The fabricated modules are tested by using a high power curve tracer. Test results verify the proposed method. 5. Simplification of the structure model of the proposed device package The package structure model is simplified through the elimination of power semiconductor device internal structure model. The simplified model can be simulated by a non-power device simulator. The simulation results of the simplified model match the simulation results of the complete model very well.en
dc.description.degreePh. D.en
dc.identifier.otheretd-03062009-163955en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-03062009-163955/en
dc.identifier.urihttp://hdl.handle.net/10919/26373en
dc.publisherVirginia Techen
dc.relation.haspartDissertation090324.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectMEDICIen
dc.subjectSiC diodeen
dc.subjectEmbedded Poweren
dc.subjectPlanar packageen
dc.subjectHigh voltageen
dc.titleTechnology for Planar Power Semiconductor Devices Package with Improved Voltage Ratingen
dc.typeDissertationen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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