Impact of Inert-electrode on the Performance and Electro-thermal Reliability of ReRAM Memory Array

While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel type of non-volatile memories, such as resistive switching memories, have lately found increased attention by both industry and academia. Resistive switching memory (ReRAM) is being considered one of the prime candidates for next-generation non-volatile memory due to relatively high switching speed, superior scalability, low power consumption, good retention and simplicity of its structure which does not require the expensive real estate structure of the silicon substrate. Furthermore, integration of ReRAM directly into a CMOS low-k/Cu interconnect module would not only reduce latency in connectivity constrained devices, but also would reduce chip's footprint by stacking memory layers on top of the logic circuits. One good candidate is the well-behaved Cu/TaOx/Pt resistive switching device. However, since platinum (Pt) acting as the inert electrode is not an economic choice for industrial production, a Back End of Line (BEOL)-compatible replacement of Pt is highly desirable. A systematic investigation has been conducted and metals such as Ru, Rh and Ir are found to be the best potential candidates to supplant Pt. The device properties of Ru, Rh and Ir based resistive switching devices have been explored in this work. However, the challenges of implementing ReRAM cell into BEOL of CMOS encompass not only the choice of materials of a CBRAM cell proper, but also the way the cell is embedded within BEOL. In case of the inert electrode, the metal interfacing the solid electrolyte (e.g. TaOx) has to be supplanted by a glue layer, and heat transport layer, leading to an engineering task of a composite electrode beyond the requirements of low miscibility with, and low surface diffusivity of the inert electrode with respect of the active metal atoms released by the active electrode (here Cu). The metal of the active electrode (Cu, Ag, Ni) is required to allow for a copious redox reaction but simultaneously preventing reactions with the dielectric. Finally, for the solid electrolyte, a dielectric with a moderate level of defects is preferred which may be controlled, for example by the deposition processes modulating the stoichiometry of the material.

This research study begins with exploration of several devices derived from the benchmark device Cu/TaOx/Pt and manufacturing those in Micron nanofabrication and characterization laboratory at Virginia Tech with the latter device used as a benchmark for performance assessment. Electric characterization of the manufactured Cu/TaOx/Ru devices has shown some notable differences between them due to the different formation, shape and rupture of the conductive filament. The inferior switching properties of the Ru device have been attributed to the substantially degraded inertness properties of the Ru electrode as a stopping barrier for Cu as compared to the Pt electrode. To study this degradation effect further, two nominally identical devices however differently embedded on the Si wafer have been fabricated. The electric behavior of the two devices are found to be markedly different and is attributed to the difference in high local temperatures in the device during the switching that cause species interlayer diffusion and trigger undesired chemical reactions. Thus, the embedment of the device has a foremost impact on the intrinsic device performance. To investigate the impact of inert electrode on the endurance of ReRAM memory cells, baseline device Cu/TaOx/Pt/Ti is compared with six devices manufactured with different inert electrode constructions: Pt/Cr, Rh/Cr, Rh/Ti, Rh/Al2O3, Ir/Ti, and Ir/Cr, while the Cu electrode and the TaOx dielectric are identical. Although the glue layers Ti, Cr or Al2O3 are not an inherent part of the device proper, they have a tangible impact on the device endurance as well. It is experimentally demonstrated that inert electrodes with high thermal conductivities have superior endurance properties over an electrode with low thermal conductivity and the heat conductivity of inert electrode has a substantial impact on ReRAM cell performance. Since reset operation is a thermally driven process, frequent switching of resistive memory cell leads to a local accumulation of Joules heat, especially when the switching rate is faster than the heat removal rate.

This investigation of local heating effects led to the exploration of non-local heat transfer within a memory array. In a crossbar arranged ReRAM cell array, heat generated in one device spreads via common electrode metal lines to the neighboring cells causing their performance degradation constituting non-local heat transfer mechanism leading to performance deterioration of neighboring cells. In addition to the electrical characterization of devices affected by the remote heat transfer, novel cell array architectures have been proposed and investigated with the goal to significantly mitigate the cell-to-cell thermal crosstalk. One of the possible mitigation measures would be modified cell erasure algorithm.