A test generation system for behaviorally modeled digital circuits

Simple item page
dc.contributor.authorLi, Wenchengen
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberBalci, Osmanen
dc.contributor.committeememberGray, F. Gailen
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.committeememberAthanas, P.M.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:19:15Zen
dc.date.adate2008-09-23en
dc.date.available2014-03-14T21:19:15Zen
dc.date.issued1996-06-15en
dc.date.rdate2008-09-23en
dc.date.sdate2008-09-23en
dc.description.abstractThis dissertation presents an approach to generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model and detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a Process Model Graph (PMG). A set of VHDL functions have been constructed to help develop VHDL models. Two algorithms are proposed to implement the test generation. <b>P-Algorithm</b> is used to generate tests at the process level. For each process a symbolic test set and the corresponding fixed valued test packages (FVTPs) are generated. Synthesis-related FVTP generation algorithms for the VHDL functions are derived to support the P-algorithm. <b>E-Algorithm</b> is employed to generate the entity level tests. The symbolic entity level tests are generated first and then the final fixed valued entity level tests are obtained by calculating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The HILO fault grader is used to generate fault coverage. Several conversion programs have been developed to support the test evaluation.en
dc.description.degreePh. D.en
dc.format.extentx, 176 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-09232008-144806en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-09232008-144806/en
dc.identifier.urihttp://hdl.handle.net/10919/39466en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V856_1996.L5.pdfen
dc.relation.isformatofOCLC# 35301092en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectVHDL modelsen
dc.subject.lccLD5655.V856 1996.L5en
dc.titleA test generation system for behaviorally modeled digital circuitsen
dc.typeDissertationen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

Files

Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
LD5655.V856_1996.L5.pdf
Size:
4.75 MB
Format:
Adobe Portable Document Format
Download

Collections

Doctoral Dissertations