Design, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devices

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dc.contributor.authorCollins, Gustina B.en
dc.contributor.committeecochairLu, Guo-Quanen
dc.contributor.committeecochairRaman, Sanjayen
dc.contributor.committeememberHendricks, Robert W.en
dc.contributor.committeememberGuido, Louis J.en
dc.contributor.committeememberScales, Wayne A.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:18:46Zen
dc.date.adate2006-12-06en
dc.date.available2014-03-14T20:18:46Zen
dc.date.issued2006-06-05en
dc.date.rdate2006-12-06en
dc.date.sdate2006-11-19en
dc.description.abstractA low-cost, low-temperature packaging concept is proposed for localized sealing and control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro- Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices require application specific packaging to facilitate their integration, provide protection from the environment, and control interactions with other circuitry. In order to integrate these devices into standard integrated circuit (IC) process flows and minimize damage due to post-fabrication steps, packaging is performed at the wafer level. In this work Indium and Silver are used to seal a monolithic localized hermetic pack- age. The cavity protecting the device is formed using standard lithography-based processing techniques. Metal walls are built up from the substrate and encapsulated by a glass or silicon lid to create a monolithic micro-hermetic package surrounding a predefined RF microsystem. The bond for the seal is then formed by rapid alloying of Indium and Silver using a temperature greater than that of the melting point of Indium. This ensures that the seal formed can subsequently function at temperatures higher than the melting temperature of pure Indium. This method offers a low-temperature bonding technique with thermal robustness suitable for wafer-level process integration. The ultimate goal is to create a seal in a vacuum environment. In this dissertation, design trade-offs made in wafer-level packaging are explained using thermo-mechanical stress and electrical performance simulations. Prototype passive microwave circuits are packaged using the developed packaging process and the performance of the fabricated circuits before and after packaging is analyzed. The effect of the package on coplanar waveguide structures are characterized by measuring scattering parameters and models are developed as a design tool for wafer-level package integration. The small scale of the localized package is expected to provide greater reliability over conventional full chip packages.en
dc.description.degreePh. D.en
dc.identifier.otheretd-11192006-102013en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11192006-102013/en
dc.identifier.urihttp://hdl.handle.net/10919/29673en
dc.publisherVirginia Techen
dc.relation.haspartfinal.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectwafer-level packagingen
dc.subjectRF MEMSen
dc.subjectMEMS Packagingen
dc.subjectmonolithic packagingen
dc.subjecthermetic packagingen
dc.subjecteutectic bondingen
dc.titleDesign, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devicesen
dc.typeDissertationen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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