Measuring and Modeling On-chip Interconnect Power on Real Hardware

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dc.contributor.authorAdhinarayanan, Vigneshen
dc.contributor.authorPaul, Indranien
dc.contributor.authorGreathouse, Joseph L.en
dc.contributor.authorHuang, Weien
dc.contributor.authorPattnaik, Ashutoshen
dc.contributor.authorFeng, Wu-chunen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.contributor.departmentComputer Scienceen
dc.date.accessioned2017-04-03T05:56:21Zen
dc.date.available2017-04-03T05:56:21Zen
dc.date.issued2016-09-26en
dc.description.abstractOn-chip data movement is a major source of power consumption in modern processors, and future technology nodes will exacerbate this problem. Properly understanding the power that applications expend moving data is vital for inventing mitigation strategies. Previous studies combined data movement energy, which is required to move information across the chip, with data access energy, which is used to read or write on- chip memories. This combination can hide the severity of the problem, as memories and interconnects will scale differently to future technology nodes. Thus, increasing the fidelity of our energy measurements is of paramount concern. We propose to use physical data movement distance as a mechanism for separating movement energy from access energy. We then use this mechanism to design microbenchmarks to ascertain data movement energy on a real modern processor. Using these microbenchmarks, we study the following parameters that affect interconnect power: (i) distance, (ii) interconnect bandwidth, (iii) toggle rate, and (iv) voltage and frequency. We conduct our study on an AMD GPU built in 28nm technology and validate our results against industrial estimates for energy/bit/millimeter. We then construct an empirical model based on our characterization and use it to evaluate the interconnect power of 22 real-world applications. We show that up to 14% of the dynamic power in some applications can be consumed by the interconnect and present a range of mitigation strategies.en
dc.description.notesBest Paper Awarden
dc.description.notesYes, full paper (Peer reviewed?)en
dc.description.notesBest Paper Awarden
dc.description.versionPublished versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.doihttps://doi.org/10.1109/IISWC.2016.7581263en
dc.identifier.isbn978-1-5090-3897-8en
dc.identifier.urihttp://hdl.handle.net/10919/76746en
dc.language.isoenen
dc.publisherIEEEen
dc.relation.ispartofIEEE International Symposium on Workload Characterizationen
dc.relation.urihttp://www.cs.vt.edu/~fengen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectGraphics Processing Units (GPUs)en
dc.subjectPower Measurementen
dc.subjectIntegrated Circuit Interconnectionsen
dc.subjectWiresen
dc.subjectCopperen
dc.subjectPower Demanden
dc.subjectPower-Aware Computingen
dc.subjectEnergy Measurementen
dc.titleMeasuring and Modeling On-chip Interconnect Power on Real Hardwareen
dc.title.serialIEEE International Symposium on Workload Characterizationen
dc.typeConference proceedingen
dc.type.dcmitypeTexten
pubs.finish-date2016-09-27en
pubs.organisational-group/Virginia Techen
pubs.organisational-group/Virginia Tech/All T&R Facultyen
pubs.organisational-group/Virginia Tech/Engineeringen
pubs.organisational-group/Virginia Tech/Engineering/COE T&R Facultyen
pubs.organisational-group/Virginia Tech/Engineering/Computer Scienceen
pubs.organisational-group/Virginia Tech/Faculty of Health Sciencesen
pubs.start-date2016-09-25en

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