SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors

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dc.contributor.authorChen, Zhiminen
dc.contributor.committeechairSchaumont, Patrick R.en
dc.contributor.committeememberHsiao, Michael S.en
dc.contributor.committeememberNazhandali, Leylaen
dc.contributor.committeememberSakiyamam, Kazuoen
dc.contributor.committeememberYao, Danfeng (Daphne)en
dc.contributor.committeememberda Silva, Claudio R. C. M.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2015-02-04T20:07:43Zen
dc.date.adate2011-07-28en
dc.date.available2015-02-04T20:07:43Zen
dc.date.issued2011-06-17en
dc.date.rdate2015-02-04en
dc.date.sdate2011-06-23en
dc.description.abstractNowadays, we use embedded electronic devices in almost every aspect of our daily lives. They represent our electronic identity; they store private information; they monitor health status; they do confidential communications, and so on. All these applications rely on cryptography and, therefore, present us a research objective: how to implement cryptography on embedded systems in a trustworthy and efficient manner. Implementing embedded cryptography faces two challenges - constrained resources and physical attacks. Due to low cost constraints and power budget constraints, embedded devices are not able to use high-end processors. They cannot run at extremely high frequencies either. Since most embedded devices are portable and deployed in the field, attackers are able to get physical access and to mount attacks as they want. For example, the power dissipation, electromagnetic radiation, and execution time of embedded cryptography enable Side-Channel Attacks (SCAs), which can break cryptographic implementations in a very short time with a quite low cost. In this dissertation, we propose solutions to efficient implementation of SCA-resistant and high-performance cryptographic software on embedded systems. These solutions make use of two state-of-the-art architectures of embedded processors: instruction set extensions and multi-core architectures. We show that, with proper processor micro-architecture design and suitable software programming, we are able to deliver SCA-resistant software which performs well in security, performance, and cost. In comparison, related solutions have either high hardware cost or poor performance or low attack resistance. Therefore, our solutions are more practical and see a promising future in commercial products. Another contribution of our research is the proper partitioning of the Montgomery multiplication over multi-core processors. Our solution is scalable over multiple cores, achieving almost linear speedup with a high tolerance to inter-core communication delays. We expect our contributions to serve as solid building blocks that support secure and high-performance embedded systems.en
dc.description.degreePh. D.en
dc.format.mediumETDen
dc.identifier.otheretd-06232011-231147en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06232011-231147/en
dc.identifier.urihttp://hdl.handle.net/10919/51256en
dc.language.isoen_USen
dc.publisherVirginia Techen
dc.relation.haspartChen_Z_D_2011.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectembedded systemsen
dc.subjectembedded securityen
dc.subjectvirtual secure circuiten
dc.subjectcryptographyen
dc.subjectpSHSen
dc.subjectside-channel attacken
dc.subjectparallel Montgomery multiplicationen
dc.titleSCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processorsen
dc.typeDissertationen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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