Optimization of Power MOSFET for High-Frequency Synchronous Buck Converter

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dc.contributor.authorBai, Yumingen
dc.contributor.committeechairHuang, Alex Q.en
dc.contributor.committeememberBoroyevich, Dushanen
dc.contributor.committeememberLai, Jih-Shengen
dc.contributor.committeememberLu, Guo-Quanen
dc.contributor.committeememberHa, Dong Samen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:16:04Zen
dc.date.adate2003-09-12en
dc.date.available2014-03-14T20:16:04Zen
dc.date.issued2003-08-28en
dc.date.rdate2006-09-12en
dc.date.sdate2003-09-09en
dc.description.abstractEvolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance. Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits. Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance.en
dc.description.degreePh. D.en
dc.identifier.otheretd-09092003-235330en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-09092003-235330/en
dc.identifier.urihttp://hdl.handle.net/10919/28915en
dc.publisherVirginia Techen
dc.relation.haspartdissertation.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectOptimizationen
dc.subjectBuck Converteren
dc.subjectTrench MOSFETen
dc.titleOptimization of Power MOSFET for High-Frequency Synchronous Buck Converteren
dc.typeDissertationen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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