Formal Descriptors for Hardware Simulation

This paper reviews the current status of an ongoing effort to develop a hardware description language which would be suitable for use as both a design tool and a documentor. Included in the requirements for this language would be the necessity for the language to function not only in many areas, such as automated design and verification, or testing and simulation, but also at many levels. That is, to range over such applications as circuit design at one end of a spectrum to the validation of systems configurations at the other end. This paper views the language requirements from three points of view, i) the subjective (human) elements usually associated with the syntactic features of the language, ii) the minimal semantic elements to be provided and the structures (both program and data) which are necessary, and iii) the features to be included in order to facilitate the formal verification of the conformance of the descriptor to preselected attributes. The work described in this paper is based on continuing research regardinq the nature of formal descriptor techniques, on their applicability to automated theorem provinq and techniques for improving the teaching of computer related languages currently under way at Virginia Polytechnic Institute and State University.