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A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

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dc.contributor.authorJudge, Lyndonen
dc.contributor.authorMane, Suvarnaen
dc.contributor.authorSchaumont, Patrick R.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2013-06-24T18:16:31Zen
dc.date.available2013-06-24T18:16:31Zen
dc.date.issued2012-09-01en
dc.description.abstractElliptic curve cryptography (ECC) has become a popular public key cryptography standard. The security of ECC is due to the difficulty of solving the elliptic curve discrete logarithm problem (ECDLP). In this paper, we demonstrate a successful attack on ECC over prime field using the Pollard rho algorithm implemented on a hardware-software cointegrated platform. We propose a high-performance architecture for multiplication over prime field using specialized DSP blocks in the FPGA. We characterize this architecture by exploring the design space to determine the optimal integer basis for polynomial representation and we demonstrate an efficient mapping of this design to multiple standard prime field elliptic curves. We use the resulting modular multiplier to demonstrate low-latency multiplications for curves secp112r1 and P-192. We apply our modular multiplier to implement a complete attack on secp112r1 using a Nallatech FSB-Compute platform with Virtex-5 FPGA. The measured performance of the resulting design is 114 cycles per Pollard rho step at 100 MHz, which gives 878 K iterations per second per ECC core. We extend this design to a multicore ECDLP implementation that achieves 14.05 M iterations per second with 16 parallel point addition cores.en
dc.description.sponsorshipThis research was supported in part by the National Science Foundation Grant no. 0644070.en
dc.description.sponsorshipThe Virginia Tech Open Access Subvention Fund subsidized the article processing fees to make this article open access.en
dc.description.versionPublished versionen
dc.format.extent15 pagesen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationLyndon Judge, Suvarna Mane, and Patrick Schaumont, “A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication,” International Journal of Reconfigurable Computing, vol. 2012, Article ID 439021, 14 pages, 2012. doi:10.1155/2012/439021en
dc.identifier.doihttps://doi.org/10.1155/2012/439021en
dc.identifier.urihttp://hdl.handle.net/10919/23259en
dc.language.isoenen
dc.publisherHindawien
dc.rightsCreative Commons Attribution 3.0 Unporteden
dc.rights.holderCopyright © 2012 Lyndon Judge et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.en
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectElliptic curve cryptography (ECC)en
dc.subjectElliptic curve discrete logarithm problem (ECDLP)en
dc.subjectPrime field arithmeticen
dc.titleA Hardware-Accelerated ECDLP with High-Performance Modular Multiplicationen
dc.title.serialInternational Journal of Reconfigurable Computingen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten

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