Browsing by Author "Boroyevich, Dushan"

Now showing 1 - 20 of 195
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    Ac-dc Bus-interface Bi-directional Converters in Renewable Energy Systems
    Dong, Dong (Virginia Tech, 2012-07-25)
    This dissertation covers several issues related to the ac-dc bus-interface bi-directional converters in renewable energy systems. The dissertation explores a dc-electronic distribution system for residential and commercial applications with a focus on the design of an ac-dc bi-directional converter for such application. This converter is named as the "Energy Control Center" due to its unique role in the system. First, the impact of the unbalanced power from the ac grid, especially the single-phase grid, on the dc system operation is analyzed. Then, a simple ac-dc two-stage topology and an advanced digital control system is proposed with a detailed design procedure. The proposed converter system significantly reduces the dc-link capacitor volume and achieves a dynamics-decoupling operation between the interfaced systems. The total volume of the two-stage topology can be reduced by upto three times compared with the typical design of a full-bridge converter. In addition, film capacitors can be used instead of electrolytic capacitors in the system, and thus the whole system reliability is improved. A set of ac passive plus active filter solutions is proposed for the ac-dc bus-interface converter which significantly reduces the total power filter volume but still eliminate the total leakage current and the common-mode conducted EMI noises by more than 90%. The dc-side low-frequency CM voltage ripple generated by the unbalanced ac voltages can be eliminated as well. The proposed solution features a high reliability and fits three types of the prevalent low-voltage ac distribution systems. Grid synchronization, a critical interface control in ac-dc bus-interface converters, is discussed in detail. First, a novel single-phase grid synchronization solution is proposed to achieve the rejection of multiple noises as well as the capability to track the ac voltage amplitude. Then, a comprehensive modeling methodology of the grid synchronization for three-phase system is proposed to explain the output frequency behaviors of grid-interface power converters at the weak grid, at the islanded condition, and at the multi-converter condition. The proposed models provide a strong tool to predict the grid synchronization instabilities raised from industries under many operating conditions, which is critical in future more-distributed-generation power systems. Islanding detection issues in ac-dc bus-interface converters are discussed in detail. More than five frequency-based islanding detection algorithms are proposed. These solutions achieve different performances and are suitable for different applications, which are advantageous over existing solutions. More importantly, the detailed modeling, trade-off analysis, and design procedures are given to help completely understand the principles. In the end, the effectiveness of the proposed solutions in a multiple-converter system are analyzed. The results drawn from the discussion can help engineers to evaluate other existing solutions as well.
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    Accurate Small-Signal Modeling for Resonant Converters
    Hsieh, Yi-Hsun (Virginia Tech, 2020-11-24)
    In comparison with PWM converters, resonant converters are gaining increasing popularity for cases in which efficiency and power density are at a premium. However, the lack of an accurate small-signal model has become an impediment to performance optimization. Many modeling attempts have been made to date. Besides the discrete time-domain modeling, most continuous-time modeling approaches are based on fundamental approximation, and are thus unable to provide sufficient accuracy for practical use. An equivalent circuit model was proposed by Yang, which works well for series resonant converters (SRCs) with high Q (quality factor), but which is inadequate for LLC resonant converters. Furthermore, the model is rather complicated, with system orders that are as high as five and seven for the SRC and LLC converter, respectively. The crux of the modeling difficulty is due to the underlying assumption based on the use of a band-pass filter for the resonant tank in conjunction with a low-pass output filter, which is not the case for most practical applications. The matter is further complicated by the presence of a rectifier, which is a nonlinearity that mixes and matches the original modulation frequency. Thus, the modulation signal becomes intractable when using a frequency-domain modeling approach. This dissertation proposes an extended describing function modeling that is based on a Fourier analysis on the continuous-time-domain waveforms. Therefore, all important contributions from harmonics are taken into account. This modeling approach is demonstrated on the frequency-controlled SRC and LLC converters. The modeling is further extended to, with great accuracy, a charge-controlled LLC converter. In the case of frequency control, a simple third-order equivalent circuit model is provided with high accuracy up to half of the switching frequency. The simplified low-frequency model consists of a double pole and a pair of right-half-plane (RHP) zeros. The double pole, when operated at a high switching frequency, manifests the property of a well-known beat frequency between the switching frequency and the resonant frequency. As the switching frequency approaches the resonant frequency of the tank, a new pair of poles is formed, representing the interaction of the resonant tank and the output filter. The pair of RHP zeros, which contributes to additional phase delay, was not recognized in earlier modeling attempts. In the case of charge control, a simple second-order equivalent circuit model is provided. With capacitor voltage feedback, the order of the system is reduced. Consequently, the resonant tank behaves as an equivalent current source and the tank property is characterized by a single pole. The other low-frequency pole represents the output capacitor and the load. However, the capacitor voltage feedback cannot eliminate the high-frequency poles and the RHP zeros. These RHP zeros may be an impediment for high-bandwidth design if not properly treated. Based on the proposed model, these unwanted RHP zeros can be mitigated by either changing the resonant tank design or by proper feedback compensation. The accurate model is essential for a high-performance high-bandwidth LLC converter.
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    Advanced Control Schemes for High-Bandwidth Multiphase Voltage Regulators
    Liu, Pei-Hsin (Virginia Tech, 2015-05-13)
    Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations. Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method. Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations. Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation. Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation. As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance.
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    Advanced Control Schemes for Voltage Regulators
    Lee, Kisun (Virginia Tech, 2008-03-28)
    The microprocessor faces a big challenge of heat dissipation. In order to enhance the performance of the microprocessor without increasing the heat dissipation, the leading microprocessor company, Intel, uses several methods to reduce the power consumption. Theses methods include enhanced sleep states control, the Speed Step technology, and multi-core architecture. These are closely related to the Voltage Regulator (VR), a dedicated power supply for the microprocessor and its control method. The speed of the VR control system should be high in order to meet the stringent load-line requirements with the high current and high di/dt, otherwise, a lot of decoupling capacitors are necessary. Capacitors make the VR cost and size higher. Therefore, the VR control method is very important. This dissertation discusses the way to increase the speed of VR without degrading other functions, such as the system efficiency, and the required control functions (AVP, current sharing and interleaving). The easiest way to increase the speed of the VR is to increase the switching frequency. However, higher switching frequency results in system efficiency degradation. This paper uses two approaches to deal with this issue. The first one is the architecture approach. The other is the fast transient control approach. For the architecture approach, a two-stage architecture is chosen. It is already shown that with a two-stage architecture, the switching frequency of the second stage can be increased, while keeping the same system efficiency. Therefore with the two-stage architecture, a high performance VR can be easily implemented. However, the light-load efficiency of two-stage architecture is not good because the bus voltage is designed for the full-load efficiency which is not optimized for the light load. The light-load efficiency is also important factor and it should be maximized because it is related to the battery life of mobile application or the energy utilization. Therefore, Adaptive Bus Voltage Positioning (ABVP) control has been proposed. By adaptively adjusting the bus voltage according to the load current, the system efficiency can be optimized for whole load range. The bus voltage rate of change is determined by the first stage bandwidth. In order to maintain regulation during a fast dynamic load, the first stage bandwidth should be high. However, it is observed from hardware when the first stage bandwidth is higher, the ABVP system can become unstable. To get a stable system, the first stage bandwidth is often designed to be slow which causes poor ABVP dynamic response. The large number of bus capacitors necessary for this also increases the size and cost. In this dissertation, in order to raise the first stage bandwidth, a stability analysis is performed. The instability loop (TABVP) is identified, and a small signal model to predict this loop is suggested. TABVP is related to the first stage bandwidth. With the higher first stage bandwidth, the peak magnitude of TABVP is larger. When the peak magnitude of TABVP touches 0dB, the system becomes unstable. Two solutions are proposed to reduce this TABVP magnitude without decreasing the first stage bandwidth. One method is to increase the feedforward gain and the other approach is to use a low pass filter. With these strategies, the ABVP system can be designed to be stable while pushing first stage bandwidth as high as possible. The ABVP-AVP system and its design are verified with hardware. For the fast transient control approach hysteretic control is chosen because of its fast transient and high light-load efficiency with DCM operation. However, in order to use the hysteretic control method for multiphase VR applications interleaving must be implemented. In this dissertation, a multiphase hysteretic control method is proposed which can achieve interleaving without losing its benefits. Using the phase locked loop (PLL), this control method locks the phase and frequency of the duty cycles to the reference clocks by modifying the size of the hysteretic band, to say, hysteretic band width. By phase shifting the reference clocks, interleaving can be achieved under steady state. During the load transient, the system loses the phase-locking function due to the slow hysteretic band width changing loop, and the system then reacts quickly to the load change without the interruption from the phase locking function (or the interleaving function). The proposed hysteretic control method consists of two loops, the fast hysteretic control loop and the slow hysteretic band width changing loop. These two nonlinear loops are difficult to model and analyze together. Therefore, assuming these two loops can be separated because of the speed difference, the phase plane model is used for the fast hysteretic control loop and the sampled data model is then used for the slow hysteretic band width changing loop. With these models, the proposed hysteretic control method can be analyzed and properly designed. However, if the transient occurs before the slow hysteretic band width changing loop settles down, the transient may start with the large hysteretic band width and the output voltage peak can exceed the specification. To prevent this, a hysteretic band width limiter is inserted. With the hardware, the proposed hysteretic control method and its design are verified. A two-phase VR with 300kHz switching frequency is built and the output capacitance required is only 860μF comparing to 1600μF output capacitance with the 50kHz bandwidth linear control method. That is about 46% capacitor reduction. The proposed hysteretic control method saturates the controller during the transient and the transient peak voltage is determined by the power stage parameters, the inductance and the output capacitors. By decreasing the inductance, the output capacitors are reduced. However, small inductance results in the low efficiency. In order to resolve this, the coupled inductor is used. With the coupled inductor, the transient inductance can be reduced with the same steady state inductance. Therefore, the transient speed can be faster without lowering down the system efficiency. The proposed hysteretic control method with the coupled inductor can be implemented using the DCR current sensing network. A two-phase VR with the proposed hysteretic control and the coupled inductor is built and the output capacitance is only 660μF comparing to 860μF output capacitance with the proposed hysteretic control only. A 23% capacitor reduction is achieved. And compared to the 50kHz bandwidth linear control method, a 60% capacitor reduction is achieved.
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    Advanced Semiconductor Device and Topology for High Power Current Source Converter
    Xu, Zhenxue (Virginia Tech, 2003-12-02)
    This dissertation presents the analysis and development of an innovative semiconductor device and topology for the high power current source converter (CSC). The CSC is very attractive in high power applications due to its lower output dv/dt, easy regeneration capability and implicit short-circuit protection. Traditionally, either a symmetrical gate turn-off (GTO) thyritor or an asymmetrical GTO in series with a diode is used as the power switch in the CSC. Since the GTO has a lower switching speed and requires a complicated gate driver, the symmetrical GTO based CSC usually has low dynamic response speed and low efficiency. To achieve high power rating, fast dynamic response speed and low harmonics, an advanced semiconductor device and topology are needed for the CSC. Based on symmetrical GTO and power MOSFET technologies, a symmetrical emitter turn-off (ETO) thyristor is developed that shows superior switching performance, high power rating and reverse voltage blocking capability. The on-state characteristics, forced turn-on characteristics, forced turn-off characteristics and the load-commutated characteristics are studied. Test results show that although the load-commutation loss is high, the developed symmetrical ETO is suitable for use in high power CSC due to its low conduction loss, fast switching speed and reverse voltage blocking capability. The snubberless turn-on capability is preferred for a semiconductor device in a power conversion system, and can be achieved for devices with forward biased safe operation area (FBSOA). The FBSOA of the ETO is investigated and experimentally demonstrated. The ETO device has excellent FBSOA due to the negative feedback provided by the emitter switch. However, the FBSOA for a large area ETO is poor. A new ETO concept is therefore proposed for future development in order to demonstrate the FBSOA over a large area device. To improve the turn-on performance of the large area ETO, a novel concept, named the transistor-mode turn-on, is proposed and studied. During the transistor-mode turn-on process, the ETO behaves like a transistor instead of a thyristor. Without a snubber, the transistor-mode turn-on for the ETO is hard to achieve. Through the selection of a proper gate drive and di/dt snubber, the transistor-mode turn-on can be implemented, and the turn-on performance for the ETO can be dramatically improved. To increase the power rating of the CSC without degrading the utilization of power semiconductor devices, a novel multilevel CSC, named the parallel-cell multilevel CSC, is proposed. Based on a six-switch CSC cell, the parallel-cell multilevel CSC has the advantages of high power rating, low harmonics, fast dynamic response and modularity. Therefore, it is very suitable for high power applications. The power stage design, modeling, control and switching modulation scheme for a parallel-cell multilevel CSC based static var compensator (STATCOM) are analyzed and verified through simulation.
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    Algorithm and implementation system for measuring impedance in the D-Q domain
    (United States Patent and Trademark Office, 2015-09-22)
    A controller and infrastructure for an impedance analyzer measures responses to perturbations to respective phases of a multi-phase system at an interface between stages thereof (which may be considered as a source and load in regard to each other), such as a multi-phase electrical power system, to determine a transfer function for each phase of the multi-phase system from which the impedance of each of the source and load can be calculated, particularly for assessing the stability of the multi-phase system.
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    An Algorithm and System for Measuring Impedance in D-Q Coordinates
    Francis, Gerald (Virginia Tech, 2010-01-25)
    This dissertation presents work conducted at the Center for Power Electronics Systems (CPES) at Virginia Polytechnic Institute and State University. Chapter 1 introduces the concept of impedance measurement, and discusses previous work on this topic. This chapter also addresses issues associated with impedance measurement. Chapter 2 introduces the analyzer architecture and the proposed algorithm. The algorithm involves locking on to the voltage vector at the point of common coupling between the analyzer and the system via a PLL to establish a D-Q frame. A series of sweeps are performed, injecting at least two independent angles in the D-Q plane, acquiring D- and Q-axis voltages and currents for each axis of injection at the point of interest. Chapter 3 discusses the analyzer hardware and the criteria for selection. The hardware built ranges from large-scale power level hardware to communication hardware implementing a universal serial bus. An eight-layer PCB was constructed implementing analog signal conditioning and conversion to and from digital signals with high resolution. The PCB interfaces with the existing Universal Controller hardware. Chapter 4 discusses the analyzer software. Software was written in C++, VHDL, and Matlab to implement the measurement process. This chapter also provides a description of the software architecture and individual components. Chapter 5 discusses the application of the analyzer to various examples. A dynamic model of the analyzer is constructed, considering all components of the measurement system. Congruence with predicted results is demonstrated for three-phase balanced linear impedance networks, which can be directly derived based on stationary impedance measurements. Other impedances measured include a voltage source inverter, Vienna rectifier, six-pulse rectifier and an autotransformer-rectifier unit.
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    Analysis and Design for a High Power Density Three-Phase AC Converter Using SiC Devices
    Lai, Rixin (Virginia Tech, 2008-12-10)
    The development of high power density three-phase ac converter has been a hot topic in power electronics area due to the increasing needs in applications like electric vehicle, aircraft and aerospace, where light weight and/or low volume is usually a must. Many challenges exist due to the complicated correlations in a three-phase power converter system. In addition, with the emerging SiC device technology the operating frequency of the converter can be potentially pushed to the range from tens of kHz to hundreds of kHz at higher voltage and higher power conditions. The extended frequency range brings opportunities to further improve the power density of the converter. Technologies based on existing devices need to be revisited. In this dissertation, a systematic methodology to analyze and design the high power density three-phase ac converter is developed. All the key factors of the converter design are explored from the high density standpoint. Firstly, the criteria for the passive filter selection are derived and the relationship between the switching frequency and the size of the EMI filter is investigated. A function integration concept as well as the physical design approach is proposed. Secondly, a topology evaluation method is presented, which provides the insight into the relationships between the system constraints, operating conditions and design variables. Four topologies are then compared with the proposed approach culminating with a favored topology under the given conditions. Thirdly, a novel average model is developed for the selected topology, and used for devising a carrier-based control approach with simple calculation and good regulation performance. Fourthly, the converter failure mode operation and corresponding protection approaches are discussed and developed. Finally, a 10 kW three-phase ac/ac converter is built with the SiC devices. All the key concepts and ideas developed in this work are implemented in this hardware system and then verified by the experimental results.
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    Analysis and Design of High-Intensity-Discharge Lamp Ballast for Automotive Headlamp
    Hu, Yongxuan (Virginia Tech, 2001-11-19)
    The High-Intensity-Discharge Lamps (HID), consisting of a broad range of gas discharge lamps, are notable for their high luminous efficacy, good color rendering, and long life. Metal halide lamps have the best combination of the above properties and are considered the most ideal light sources. Recently, there has been an emerging demand to replace the conventional halogen headlamps with the newly introduced small-wattage metal halide HID lamps. However, this lamp demands a highly efficient ballast and very complex control circuitry that can achieve fast turn-on and different regulation modes during the lamp start-up process. Due to the complex lamp v-i profile and timing control requirements, control circuit built with conventional analog control is unavoidably cumbersome. With the unparalleled flexibility and programmability, digital control shows more advantages in this application. An automotive HID ballast with digital controller is developed to demonstrate the feasibility of the digital control along with some key issues in digital controller selection and design. Results show that the microcontroller-based HID ballast can successfully realize the required control functions and achieve a smooth turn-on process and a fast turn-on time of 8 seconds. One of the major issues of ballast design is the ballast/HID lamp system stability, which originates from the lamp negative incremental impedance. The lamp small-signal model is presented with simulation and measurements. The negative incremental impedance is attributed to a RHP zero in the small-signal model. A new analysis approach, impedance ratio criterion, is proposed to analyze the system stability. With this approach, it clearly shows how the control configurations and converter and control design affect the system stability. The results can provide guidance and be easily used in control configuration selection and converter and control design. Analysis shows that ballast based on PWM converter without inner current loop is unstable and with inner current loop can stabilized the system. This is the reason why for a microcontroller-based ballast system the inner current loop has to be used. HID lamp has its special acoustic resonance problem and thus a low-frequency unregulated full-bridge is used following the front-end DC/DC converter. To prevent from lamp re-igniting during each bridge commutation, a minimum current changing slope has to be guaranteed. In order to help design the converter, the ballast/lamp re-ignition analysis is presented. With this analysis, it shows that the output capacitance has to be small enough to ensure adequate current slope during zero crossing. Though some approximation is used to simplify the analysis, the results can provide qualitative guidance in the ballast design.
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    Analysis and Design of Paralleled Three-Phase Voltage Source Converters with Interleaving
    Zhang, Di (Virginia Tech, 2010-04-26)
    Three-phase voltage source converters(VSCs) have become the converter of choice in many ac medium and high power applications due to their many advantages, including low harmonics, high power factor, and high efficiency. Modular VSCs have also been a popular choice as building blocks to achieve even higher power, primarily through converter paralleling. In addition to high power ratings, paralleling converters can also provide system redundancy through the so-called (N+1) configuration for improved availability, as well as allow easy implementation of converter power management. Interleaving can further improve the benefit of paralleling VSCs by reducing system harmonic currents, which potentially can increase system power density. There are many challenges to implement interleaving in paralleled VSCs system due to the complicated relationships in a three-phase power converter system. In addition, to maximize the benefit of interleaving, current knowledge of symmetric interleaving is not enough. More insightful understanding of this PWM technology is necessary before implement interleaving in a real paralleled VSCs system. In this dissertation, a systematic methodology to analyze and design a paralleled three-phase voltage source converters with interleaving is developed. All the analysis and proposed control methods are investigated with the goal of maximizing the benefit of interleaving based on system requirement. The dissertation is divided into five sections. Firstly, a complete analysis studying the impact of interleaving on harmonic currents in ac and dc side passive components for paralleled VSCs is presented. The analysis performed considers the effects of modulation index, pulse-width-modulation (PWM) schemes, interleaving angle and displacement angle. Based on the analysis the method to optimize interleaving angle is proposed. Secondly, the control methods for the common mode (CM) circulating current of paralleled three-phase VSCs with discontinuous space-vector modulation (DPWM) and interleaving are proposed. With the control methods, DPWM and interleaving, which is a desirable combination, but not considered possible, can be implemented together. In addition, the total flux of integrated inter-phase inductor to limit circulating current can be minimized. Thirdly, a 15 kW three phase ac-dc rectifier is built with SiC devices. With the technologies presented in this dissertation, the specific power density can be pushed more than 2kW/lb. Fourthly, the converter system with low switching frequency is studied. Special issues such as beat phenomenon and system unbalance due to non-triplen carrier ratio is explained and solved by control methods. Other than that, an improved asymmetric space vector modulation is proposed, which can significantly reduce output current total harmonic distortion (THD) for single and interleaved VSCs system. Finally, the method to protect a system with paralleled VSCs under the occurrence of internal faults is studied. After the internal fault is detected and isolated, the paralleled VSCs system can continue work. So system reliability can be increased.
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    Analysis and Evaluation of Soft-switching Inverter Techniques in Electric Vehicle Applications
    Dong, Wei (Virginia Tech, 2003-04-22)
    This dissertation presents the systematic analysis and the critical assessment of the AC side soft-switching inverters in electric vehicle (EV) applications. Although numerous soft-switching inverter techniques were claimed to improve the inverter performance, compared with the conventional hard-switching inverter, there is the lack of comprehensive investigations of analyzing and evaluating the performance of soft-switching inverters. Starting with an efficiency comparison of a variety of the soft-switching inverters using analytical calculation, the dissertation first reveals the effects of the auxiliary circuit's operation and control on the loss reduction. Three types of soft-switching inverters realizing the zero-voltage-transition (ZVT) or zero-current-transition (ZCT) operation are identified to achieve high efficiency operation. Then one hard-switching inverter and the chosen soft-switching inverters are designed and implemented with the 55 kW power rating for the small duty EV application. The experimental evaluations on the dynamometer provide the accurate description of the performance of the soft-switching inverters in terms of the loss reductions, the electromagnetic interference (EMI) noise, the total harmonic distortion (THD) and the control complexity. An analysis of the harmonic distortion caused by short pulses is presented and a space vector modulation scheme is proposed to alleviate the effect. To effectively analyze the soft-switching inverters' performance, a simulation based electrical modeling methodology is developed. Not only it extends the EMI noise analysis to the higher frequency region, but also predicts the stress and the switching losses accurately. Three major modeling tasks are accomplished. First, to address the issues of complicated existing scheme, a new parameter extraction scheme is proposed to establish the physics-based IGBT model. Second, the impedance based measurement method is developed to derive the internal parasitic parameters of the half-bridge modules. Third, the finite element analysis software is used to develop the model for the laminated bus bar including the coupling effects of different phases. Experimental results from the single-leg operation and the three-phase inverter operation verify the effectiveness of the presented systematic electrical modeling approach. With the analytical tools verified by the testing results, the performance analysis is further extended to different power ratings and different bus voltage designs.
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    Analysis of Direct-Soldered Power Module / Heat Sink Thermal Interface for Electric Vehicle Applications
    Kim, Junhyung (Virginia Tech, 2001-04-27)
    Reducing the thermal impedance between power module and heat sink is important for high-power density, low-cost inverter applications. Mounting a power module by directly soldering it onto a heat sink can significantly reduce the thermal impedance at the module / heat sink interface, as compared to the conventional method of bolting the two together with a thermal grease or some other interface materials in between. However, a soldered interface typically contains a large number of voids, which results in local hot spots. This thesis describes approaches taken to reduce voids in the solder layer through surface treatment, solder paste selection, and adjustment in solder-reflow conditions. A 15MHz scanning acoustic microscope (SAM), a non-destructive inspection tool, was used to determine the void content at the module / heat sink interface. The experimental results show that a significant reduction in thermal resistance can be achieved by reducing the void content at the soldered module / heat sink interface. Moreover, a comparison of the thermal resistances in cases using the worst soldering, which contains the largest voided area, ThermstrateTM and thermal grease are presented. Thermal performances of the modules are studied by simulation with Flotherm.
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    Analysis of Inductor-Coupled Zero-Voltage-Transition Converters
    Choi, Jae-Young (Virginia Tech, 2001-07-24)
    As is the case for DC-DC converters, multi-phase converters require both high-quality power control and high power-density. Although a higher switching frequency not only improves the quality of the converter output but also decreases the size of the converter, it increases switching losses and electromagnetic interference (EMI) noise. Since the soft-switching topologies reduce the switching losses of the converter main switches, the topologies make converters partially independent from the switching frequency. However, the conventional soft-switching topologies have already proposed most of the possible ways to improve converter performance. In addition, the trends of the newly generated power devices reduce the advantages of soft-switching topologies. This critical situation surrounding soft-switching topologies gives research motivations: What features of soft-switching topologies facilitate their practical applications? Given this motivation, the dissertation discusses two aspects = simplifying auxiliary circuits and accounting for the effects of soft-switching operations on the converter control. Engineers working with medium- and high-power multi-phase converters require simplified soft-switching topologies that have the same level of performance as the conventional soft-switching topologies. This demand is the impetus behind one of the research objectives = simplifying the auxiliary circuits of Zero-Voltage-Transition (ZVT) inverters. Simplifying the auxiliary circuits results in both a smaller number of and lower cost for auxiliary components, without any negative impact on performance. This dissertation proposes two major concepts for the simplification - the Single-Switch Single-Leg (S3L) ZVT cell and the Phase-Lock (PL) concept. Throughout an effort to eliminate circulating currents of inductor-coupled (IC) ZVT converters, the S3L ZVT cell is developed. The proposed cell allows a single auxiliary switch to achieve zero-voltage conditions for both the top and bottom main switches, and it achieves the same level of performance as the conventional ZVT cell, as well. This proposal makes IC ZVT topologies more attractive to multi-phase converter applications. Because all of the top main switches generally have identical sequences for zero-voltage turn-on commutations, one auxiliary switch might handle the commutations of all of the top main switches. This possibility introduces the PL concept, which allows the two auxiliary switches to provide a zero-voltage condition for any main switch commutation. In order to compensate for restrictions of this concept, a modified space-vector modulation (SVM) scheme also is introduced. A soft-switching topology changes the duty ratios of the converter, which affects the controllability of the converter. Therefore, this dissertation selects resolution of this issue as one of the research objectives. This dissertation derives the generalized timing equations of ZVT operations, and the generalized equations formulize the effect of ZVT operation on both duty ratios and DC current. Moreover, the effect of SVM schemes is also investigated. An average model of the ZVT converter is developed using both the timing analysis and the investigation of SVM schemes, and small-signal analysis using the average model predicts the steady-state characteristics of the converter.
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    Analysis of the Power Conditioning System for a Superconducting Magnetic Energy Storage Unit
    Superczynski, Matthew J. (Virginia Tech, 2000-07-24)
    Superconducting Magnetic Energy Storage (SMES) has branched out from its application origins of load leveling, in the early 1970s, to include power quality for utility, industrial, commercial and military applications. It has also shown promise as a power supply for pulsed loads such as electric guns and electromagnetic aircraft launchers (EMAL) as well as for vital loads when power distribution systems are temporarily down. These new applications demand more efficient and compact high performance power electronics. A 250 kW Power Conditioning System (PCS), consisting of a voltage source converter (VSC) and bi-directional two-quadrant DC/DC converter (chopper), was developed at the Center for Power Electronics Systems (CPES) under an ONR funded program. The project was to develop advanced power electronic techniques for SMES Naval applications. This thesis focuses on system analysis and development of a demonstration test plan to illustrate the SMES systems' ability to be multitasked for implementation on naval ships. The demonstration focuses on three applications; power quality, pulsed power and vital loads. An integrated system controller, based on an Altera programmable logic device, was developed to coordinate charge/discharge transitions. The system controller integrated the chopper and VSC controller, configured applicable loads, and dictated sequencing of events during mode transitions. Initial tests with a SMES coil resulted in problems during mode transitions. These problems caused uncontrollable transients and caused protection to trigger and processors to shut down. Accurate models of both the Chopper and VSC were developed and an analysis of these mode transition transients was conducted. Solutions were proposed, simulated and implemented in hardware. Successful operation of the system was achieved and verified with both a low temperature superconductor here at CPES and a high temperature superconductor at The Naval Research Lab.
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    Analysis, simulation and modeling of three-level VSIs
    Cosan, Muhammet (Virginia Tech, 1997-11-05)
    Analysis of three-phase, three-level VSIs is done for high-power high-voltage applications. Complete Space Vector Modulation (SVM) algorithm is developed for a three-phase, three-level converter. Special attention is given to minimization of output ripple and voltage balance of the dc-link input capacitors. Verification of the proposed SVM algorithm is done by computer simulation. Comprehensive small-signal modeling of the three-level converter with a resistive load is developed the first time. Steady-state solutions reveal that the voltage across dc-link input capacitors is constant at the half of the dc-link voltage.
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    Anti-islanding detection for three-phase distributed generation
    (United States Patent and Trademark Office, 2017-04-25)
    Wobbling the operating frequency of a phase-locked loop (PLL), preferably by adding a periodic variation is feedback gain or delay in reference signal phase allows the avoidance of any non-detection zone that might occur due to exact synchronization of the phase locked loop operating frequency with a reference signal. If the change in PLL operating frequency is periodic, it can be made of adequate speed variation to accommodate and time requirement for islanding detection or the like when a reference signal being tracked by the PLL is lost. Such wobbling of the PLL operating frequency is preferably achieved by addition a periodic variable gain in a feedback loop and/or adding a periodically varying phase delay in a reference signal and/or PLL output.
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    Application of High-Power Snubberless Semiconductor Switches in High-Frequency PWM Converters
    Motto, Kevin (Virginia Tech, 2000-11-21)
    For many years, power electronics in the high-power area was performed with extremely slow semiconductor switches. These switches, including the thyristor and the Gate Turn-Off (GTO) thyristor, had the capacity to handle very high voltages and currents but lacked the ability to perform high frequency switching. Low-power converters, such as computer power supplies and low horsepower motor drives, have employed high-frequency switching for years and have benefited from very nice output waveforms, good control dynamic performance, and many other advantages compared to low frequency switching. Recent improvements in high-power semiconductor technology has brought switching performance similar to that of the low-power MOSFETs and IGBTs to the high-power area through the advancement of the IGBT's ratings to create the High Voltage IGBT (HVIGBT) and the development of new GTO-derived devices including the Integrated Gate Commutated Thyristor (IGCT) and the Emitter Turn-Off (ETO) thyristor. These new devices all feature high switching speed and the capability to turn off without the requirement for a turn-off snubber. With these new device technologies the high-power field of power electronics can realize dramatic improvements in the performance of systems for utility applications and motor drives. However, with these high-speed switches come new issues relating to noise, protection, performance of diodes, and thermal management in high-frequency applications. This thesis addresses the application of these new devices, especially the ETO and the IGCT. Examples of each device technology (IGBT, IGCT, and ETO) have been characterized in both their switching performance and conduction loss. The tests performed show how these new devices may be applied to various applications. The switching loss, especially related to turn-off, is the dominant factor in the power dissipation of the high-power switches, so knowledge of these characteristics are very important in the system design. To demonstrate the operation of the ETO, two power converters were constructed. The first was a 100 kW DC/DC converter, which demonstrated the operation of the ETO in a typical building block configuration, the half-bridge. The second system, a 1 MegaVolt-Amp (MVA) three-phase inverter, demonstrated the ETO in an application where the switching frequency and power level were both high. The test results demonstrate the expected characteristics of the high-frequency converters. The development of the ETO's gate driver is described. During the inverter testing, a new failure mode was found involving a parasitic diode within the ETO. This failure mode was analyzed and solutions were proposed. One of the proposed solutions was implemented and there were no more failures of this type. Another possible failure mode regarding a circulating current in an IGCT-based system is also analyzed. Soft-switching techniques can help reduce the switching loss in power semiconductor switches. Several topologies were considered for application in the high-power area, and one was selected for further investigation. A prototype Zero Current Transition (ZCT) circuit was developed using an IGCT as the main switch. The turn-off loss was reduced dramatically through the tested ZCT circuit, and the diode recovery was also alleviated.
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    Application of Optimization Techniques to the Design of a Boost Power Factor Correction Converter
    Busquets-Monge, Sergio (Virginia Tech, 2001-07-02)
    This thesis analyzes the procedural approach and benefits of applying optimization techniques to the design of a boost power factor correction (PFC) converter with an input electromagnetic interference (EMI) filter at the component level. The analysis is performed based on the particular minimum cost design study of a 1.15 kW unit satisfying a set of specifications. A traditional design methodology is initially analyzed and employed to obtain a first design. A continuous design optimization is then formulated and solved to gain insight into the converter design tradeoffs and particularities. Finally, a discrete optimization approach using a genetic algorithm is defined to develop a completely automated user-friendly software design tool able to provide in a short period of time globally optimum designs of the system for different sets of specifications. The software design tool is then employed to optimize the system design, and the savings with respect to the traditional design methodology are highlighted. The optimization problem formulation in both the continuous and discrete cases is presented in detail. The system design variables, objective function (system component cost) and constraints are identified. The objective function is expressed as a function of the design variables. A computationally efficient and experimentally validated model of the system, including second-order effects, allows the constraint values (also as a function of the design variables) to be obtained.
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    Bayesian Optimization of PCB-Embedded Electric-Field Grading Geometries for a 10 kV SiC MOSFET Power Module
    Cairnie, Mark A. Jr. (Virginia Tech, 2021-04-28)
    A finite element analysis (FEA) driven, automated numerical optimization technique is used to design electric field grading structures in a PCB-integrated bus bar for a 10 kV bondwire-less silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, careful design of field-grading structures inside the bus bar is required to mitigate the high electric field strength in the air. Using Bayesian optimization and a new weighted point-of-interest (POI) cost function, the highly non-uniform electric field is efficiently optimized without the use of field integration, or finite-difference derivatives. The proposed optimization technique is used to efficiently characterize the performance of the embedded field grading structure, providing insights into the fundamental limitations of the system. The characterization results are used to streamline the design and optimization of the bus bar and high-density module interface. The high-density interface experimentally demonstrated a partial discharge inception voltage (PDIV) of 11.6 kV rms. When compared to a state-of-the-art descent-based optimization technique, the proposed algorithm converges 3x faster and with 7x smaller error, making both the field grading structure and the design technique widely applicable to other high-density high-voltage design problems.
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    Behavioral EMI-Models of Switched Power Converters
    Bishnoi, Hemant (Virginia Tech, 2013-11-05)
    Measurement-based behavioral electromagnetic interference (EMI) models have been shown earlier to accurately capture the EMI behavior of switched power converters. These models are compact, linear, and run in frequency domain, enabling faster and more stable simulations compared to the detailed lumped circuit models. So far, the behavioral EMI modeling techniques are developed and applied to the converter's input side only. The resulting models are therefore referred to as "terminated EMI models". Under the condition that the output side of the converter remains fixed, these models can predict the input side EMI for any change in the impedance of the input side network. However, any change at the output side would require re-extraction of the behavioral model. Thus the terminated EMI models are incapable of predicting the change in the input side EMI due to changes at the output side of the converter or vice versa. The above mentioned limitation has been overcome by an "un-terminated EMI model" proposed in this dissertation. Un-terminated EMI models are developed here to predict both the common-mode (CM) and the differential (DM) noise currents at the input and the output sides of a motor-drive system. The modeling procedure itself has been simplified and now requires fewer measurements and results in less noise in the identified model parameters. Both CM and DM models are then combined to predict the total noise in the motor drive system. All models are validated by experiments and their limitations identified. A significant portion of this dissertation is then devoted to the application of behavioral EMI models in the design of EMI filters. Comprehensive design procedures are developed for both DM and CM filters in a motor-drive system. The filters designed using the proposed methods are experimentally shown to satisfy the DO-160 conducted emissions standards. The dissertation ends with a summary of contributions, limitations, and some future research directions.