An Algorithm and System for Measuring Impedance in D-Q Coordinates

This dissertation presents work conducted at the Center for Power Electronics Systems (CPES) at Virginia Polytechnic Institute and State University.

Chapter 1 introduces the concept of impedance measurement, and discusses previous work on this topic. This chapter also addresses issues associated with impedance measurement.

Chapter 2 introduces the analyzer architecture and the proposed algorithm. The algorithm involves locking on to the voltage vector at the point of common coupling between the analyzer and the system via a PLL to establish a D-Q frame. A series of sweeps are performed, injecting at least two independent angles in the D-Q plane, acquiring D- and Q-axis voltages and currents for each axis of injection at the point of interest.

Chapter 3 discusses the analyzer hardware and the criteria for selection. The hardware built ranges from large-scale power level hardware to communication hardware implementing a universal serial bus. An eight-layer PCB was constructed implementing analog signal conditioning and conversion to and from digital signals with high resolution. The PCB interfaces with the existing Universal Controller hardware.

Chapter 4 discusses the analyzer software. Software was written in C++, VHDL, and Matlab to implement the measurement process. This chapter also provides a description of the software architecture and individual components.

Chapter 5 discusses the application of the analyzer to various examples. A dynamic model of the analyzer is constructed, considering all components of the measurement system. Congruence with predicted results is demonstrated for three-phase balanced linear impedance networks, which can be directly derived based on stationary impedance measurements. Other impedances measured include a voltage source inverter, Vienna rectifier, six-pulse rectifier and an autotransformer-rectifier unit.