Browsing by Author "Francis, Gerald"

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    Algorithm and implementation system for measuring impedance in the D-Q domain
    (United States Patent and Trademark Office, 2015-09-22)
    A controller and infrastructure for an impedance analyzer measures responses to perturbations to respective phases of a multi-phase system at an interface between stages thereof (which may be considered as a source and load in regard to each other), such as a multi-phase electrical power system, to determine a transfer function for each phase of the multi-phase system from which the impedance of each of the source and load can be calculated, particularly for assessing the stability of the multi-phase system.
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    An Algorithm and System for Measuring Impedance in D-Q Coordinates
    Francis, Gerald (Virginia Tech, 2010-01-25)
    This dissertation presents work conducted at the Center for Power Electronics Systems (CPES) at Virginia Polytechnic Institute and State University. Chapter 1 introduces the concept of impedance measurement, and discusses previous work on this topic. This chapter also addresses issues associated with impedance measurement. Chapter 2 introduces the analyzer architecture and the proposed algorithm. The algorithm involves locking on to the voltage vector at the point of common coupling between the analyzer and the system via a PLL to establish a D-Q frame. A series of sweeps are performed, injecting at least two independent angles in the D-Q plane, acquiring D- and Q-axis voltages and currents for each axis of injection at the point of interest. Chapter 3 discusses the analyzer hardware and the criteria for selection. The hardware built ranges from large-scale power level hardware to communication hardware implementing a universal serial bus. An eight-layer PCB was constructed implementing analog signal conditioning and conversion to and from digital signals with high resolution. The PCB interfaces with the existing Universal Controller hardware. Chapter 4 discusses the analyzer software. Software was written in C++, VHDL, and Matlab to implement the measurement process. This chapter also provides a description of the software architecture and individual components. Chapter 5 discusses the application of the analyzer to various examples. A dynamic model of the analyzer is constructed, considering all components of the measurement system. Congruence with predicted results is demonstrated for three-phase balanced linear impedance networks, which can be directly derived based on stationary impedance measurements. Other impedances measured include a voltage source inverter, Vienna rectifier, six-pulse rectifier and an autotransformer-rectifier unit.
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    A Synchronous Distributed Digital Control Architecture for High Power Converters
    Francis, Gerald (Virginia Tech, 2004-03-03)
    Power electronics applications in high power are normally large, expensive, spatially distributed systems. These systems are typically complex and have multiple functions. Due to these properties, the control algorithm and its implementation are challenging, and a different approach is needed to avoid customized solutions to every application while still having reliable sensor measurements and converter communication and control. This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller.