Browsing by Author "Lee, Fred C."

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    48V/1V Voltage Regulator for High-Performance Microprocessors
    Lou, Xin (Virginia Tech, 2024-06-07)
    The data center serves as the hardware foundation for artificial intelligence (AI) and cloud computing, constituting a global market that has surpassed $200 billion and is experiencing rapid growth. It is estimated that data centers contribute to 1.7-2.2% of the world's electricity generation. Conversely, up to 80% of the long-term operational expenditure of data centers is allocated to electricity consumption. Consequently, enhancing the efficiency of electric energy conversion in data centers is not only economically advantageous but also crucial for achieving carbon-neutral objectives. Through collaborative efforts between the industrial and academic sectors, substantial advancements have been achieved in the energy conversion efficiency of data centers. Most converters within the data center power architecture now boast efficiencies exceeding 99%. However, the bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs), given their heightened power demands compared to conventional central processing units (CPUs). To enhance system efficiency, a revolutionary shift in power architecture has been introduced, advocating for the adoption of a 48 V data center power architecture to replace the conventional 12 V architecture. The higher 48 V bus voltage significantly reduces distribution loss on the bus. However, the primary challenge lies in managing high step-down voltage conversion while maintaining high efficiency. Additionally, high-performance microprocessors, including CPUs, GPUs, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs), require hundreds of amperes of current at low voltage levels (e.g., GPUs need >220 A at <1.85 V, CPUs need >1000 A at <1.0 V). An unavoidable consequence of upscaling processor current and size is the substantial resistive loss in VRMs. This is because such loss scales with the square of the current [I2R], and the power path area (and resistance R) expands with the processor size. The Power Delivery Network (PDN) resistance in the "last inch" of the power delivery path is becoming a limiting factor in processor performance and system efficiency. The key to reducing the I2R loss is minimizing the distance between the VRMs and processors by utilizing ultra-high power density VRMs. Furthermore, the design of Voltage Regulator Modules (VRMs) for high-performance microprocessors encounters additional formidable challenges, especially when dealing with the requirements of contemporary computing architectures. The key hurdles encompass achieving high efficiency, handling low output voltage, accommodating wide voltage ranges, managing elevated output currents, and addressing significant load transients. These challenges prompt both academia and industry to explore novel topologies, innovative magnetic integration methods, and advanced control strategies. The prevailing trend in state-of-the-art 48V solutions centers around the adoption of two-stage configurations, wherein the second stage can leverage conventional 12V solutions. However, this approach imposes limitations on power density and efficiency, given that power traverses two cascaded DC/DC converters. Additionally, the footprint of decoupling capacitors and I2R loss on the intermedia bus between the two stages is emerging as a noteworthy consideration in designs. In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. Initially, a single-stage coupled-transformer voltage regulator (CTVR) with discrete magnetics is presented, offering a 48V solution while maintaining a comparable size and cost to a state-of-the-art 12V multiphase buck regulator. Leveraging the indirect-coupling concept, magnetic components are standardized, enabling scalability and facilitating multiphase operation. A prototype is constructed and tested to validate the CTVR's performance. With a 48V input and 1.8V output, the peak efficiency registers at 92.1%, and the power area density is 0.45 W/mm2. However, voltage ringing is observed in both primary and secondary switches due to a larger leakage inductance and hard-switching operation. Subsequently, a transition to soft-switching operation is implemented to address the voltage ringing issue. The leakage inductance is intentionally designed to supply energy for zero-voltage switching (ZVS) of primary switches, turning the previously perceived drawback into an opportunity for efficiency improvement. As a result, testing demonstrates a peak efficiency increase of more than 1%, reaching 93.6%. Furthermore, efforts are made to enhance small leakage inductance by employing well-interleaved printed circuit board (PCB) windings. Following a series of design optimizations, the prototype achieves a peak efficiency of 93.1% and a remarkable power density of 1037 W/in3, accounting for gate driver loss and size. Despite an increase in cost associated with PCB windings, this proposed solution attains the highest power density and stands as the pioneering 48V single-stage design surpassing 1000 W/in3 power density. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results.
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    6.78MHz Omnidirectional Wireless Power Transfer System for Portable Devices Application
    Feng, Junjie (Virginia Tech, 2021-01-11)
    Wireless power transfer (WPT) with loosely coupled coils is a promising solution to deliver power to a battery in a variety of applications. Due to its convenience, wireless power transfer technology has become popular in consumer electronics. Thus far, the majority of the coupled coils in these systems are planar structure, and the magnetic field induced by the transmitter coil is in one direction, meaning that the energy power transfer capability degrades greatly when there is some angle misalignment between the coupled coils. To improve the charging flexibility, a three–dimensional (3D) coils structure is proposed to transfer energy in different directions. With appropriate modulation current flowing through each transmitter coil, the magnetic field rotates in different directions and covers all the directions in 3D space. With omnidirectional magnetic field, the charging platform can provide energy transfer in any direction; therefore, the angle alignment between the transmitter coil and receiver coil is no longer needed. Compensation networks are normally used to improve the power transfer capability of a WPT system with loosely coupled coils. The resonant circuits, formed by the loosely coupled coils and external compensation inductors or capacitors, are crucial in the converter design. In WPT system, the coupling coefficient between the transmitting coil and the receiving coil is subject to the receiver's positioning. The variable coupling condition is a big challenge to the resonant topology selection. The detailed requirements of the resonant converter in an omnidirectional WPT system are identified as follows: 1). coupling independent resonant frequency; 2). load independent output voltage; 3). load independent transmitter coil current; 4). maximum efficiency power transfer; 5). soft switching of active devices. A LCCL-LC resonant converter is derived to satisfy all of the five requirements. In consumer electronics applications, Megahertz (MHz) WPT systems are used to improve the charging spatial freedom. 6.78 MHz is selected as the system operation in AirFuel standard, a wireless charging standard for commercial electronics. The zero voltage switching (ZVS) operation of the switching devices is essential in reducing the switching loss and the switching related electromagnetic interference (EMI) issue in a MHz system; therefore, a comprehensive evaluation of ZVS condition in an omnidirectional WPT system is performed. And a design methodology of the LCCL-LC converter to achieve ZVS operation is proposed. The big hurdle of the WPT technology is the safety issue related to human exposure of electromagnetic fields (EMF). A double layer shield structure, including a magnetic layer and a conductive layer, is proposed in a three dimensional charging setup to reduce the stray magnetic field level. A parametric analysis of the double shield structure is conducted to improve the attenuation capability of the shielding structure. In an omnidirectional WPT system, the energy can be transferred in any direction; however the receiving devices has its preferred field direction based on its positioning and orientation. To focus power transfer towards targeted loads, a smart detection algorithm for identifying the positioning and orientation of receiver devices based on the input power information is presented. The system efficiency is further improved by a maximum efficiency point tracking function. A novel power flow control with a load combination strategy to charge multiple loads simultaneously is explained. The charging speed of the omnidirectional WPT system is greatly improved with proposed power flow control.
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    Ac-dc Bus-interface Bi-directional Converters in Renewable Energy Systems
    Dong, Dong (Virginia Tech, 2012-07-25)
    This dissertation covers several issues related to the ac-dc bus-interface bi-directional converters in renewable energy systems. The dissertation explores a dc-electronic distribution system for residential and commercial applications with a focus on the design of an ac-dc bi-directional converter for such application. This converter is named as the "Energy Control Center" due to its unique role in the system. First, the impact of the unbalanced power from the ac grid, especially the single-phase grid, on the dc system operation is analyzed. Then, a simple ac-dc two-stage topology and an advanced digital control system is proposed with a detailed design procedure. The proposed converter system significantly reduces the dc-link capacitor volume and achieves a dynamics-decoupling operation between the interfaced systems. The total volume of the two-stage topology can be reduced by upto three times compared with the typical design of a full-bridge converter. In addition, film capacitors can be used instead of electrolytic capacitors in the system, and thus the whole system reliability is improved. A set of ac passive plus active filter solutions is proposed for the ac-dc bus-interface converter which significantly reduces the total power filter volume but still eliminate the total leakage current and the common-mode conducted EMI noises by more than 90%. The dc-side low-frequency CM voltage ripple generated by the unbalanced ac voltages can be eliminated as well. The proposed solution features a high reliability and fits three types of the prevalent low-voltage ac distribution systems. Grid synchronization, a critical interface control in ac-dc bus-interface converters, is discussed in detail. First, a novel single-phase grid synchronization solution is proposed to achieve the rejection of multiple noises as well as the capability to track the ac voltage amplitude. Then, a comprehensive modeling methodology of the grid synchronization for three-phase system is proposed to explain the output frequency behaviors of grid-interface power converters at the weak grid, at the islanded condition, and at the multi-converter condition. The proposed models provide a strong tool to predict the grid synchronization instabilities raised from industries under many operating conditions, which is critical in future more-distributed-generation power systems. Islanding detection issues in ac-dc bus-interface converters are discussed in detail. More than five frequency-based islanding detection algorithms are proposed. These solutions achieve different performances and are suitable for different applications, which are advantageous over existing solutions. More importantly, the detailed modeling, trade-off analysis, and design procedures are given to help completely understand the principles. In the end, the effectiveness of the proposed solutions in a multiple-converter system are analyzed. The results drawn from the discussion can help engineers to evaluate other existing solutions as well.
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    Accelerated commutation for passive clamp isolated boost converters
    (United States Patent and Trademark Office, 2005-04-05)
    An efficient and cost effective bidirectional DC/DC converter reduces switch voltage stress via accelerated commutation allowing use of a low-cost passive clamp circuit in boost mode. The converter includes a primary circuit, transformer and secondary circuit. The primary circuit takes the form of a “full bridge converter,” a “push-pull converter,” or an “L-type converter.”. The primary circuit may include a dissipator such as a snubber circuit or small buck converter. A secondary side of the transformer is momentarily shorted by the secondary circuit by, for example, turning on at least two switches in the secondary circuit simultaneously for a minimal calibratable period when a pair of primary circuit controllers turn off to protect the primary circuit switches from voltage spikes during switching conditions.
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    Accurate Small-Signal Modeling for Resonant Converters
    Hsieh, Yi-Hsun (Virginia Tech, 2020-11-24)
    In comparison with PWM converters, resonant converters are gaining increasing popularity for cases in which efficiency and power density are at a premium. However, the lack of an accurate small-signal model has become an impediment to performance optimization. Many modeling attempts have been made to date. Besides the discrete time-domain modeling, most continuous-time modeling approaches are based on fundamental approximation, and are thus unable to provide sufficient accuracy for practical use. An equivalent circuit model was proposed by Yang, which works well for series resonant converters (SRCs) with high Q (quality factor), but which is inadequate for LLC resonant converters. Furthermore, the model is rather complicated, with system orders that are as high as five and seven for the SRC and LLC converter, respectively. The crux of the modeling difficulty is due to the underlying assumption based on the use of a band-pass filter for the resonant tank in conjunction with a low-pass output filter, which is not the case for most practical applications. The matter is further complicated by the presence of a rectifier, which is a nonlinearity that mixes and matches the original modulation frequency. Thus, the modulation signal becomes intractable when using a frequency-domain modeling approach. This dissertation proposes an extended describing function modeling that is based on a Fourier analysis on the continuous-time-domain waveforms. Therefore, all important contributions from harmonics are taken into account. This modeling approach is demonstrated on the frequency-controlled SRC and LLC converters. The modeling is further extended to, with great accuracy, a charge-controlled LLC converter. In the case of frequency control, a simple third-order equivalent circuit model is provided with high accuracy up to half of the switching frequency. The simplified low-frequency model consists of a double pole and a pair of right-half-plane (RHP) zeros. The double pole, when operated at a high switching frequency, manifests the property of a well-known beat frequency between the switching frequency and the resonant frequency. As the switching frequency approaches the resonant frequency of the tank, a new pair of poles is formed, representing the interaction of the resonant tank and the output filter. The pair of RHP zeros, which contributes to additional phase delay, was not recognized in earlier modeling attempts. In the case of charge control, a simple second-order equivalent circuit model is provided. With capacitor voltage feedback, the order of the system is reduced. Consequently, the resonant tank behaves as an equivalent current source and the tank property is characterized by a single pole. The other low-frequency pole represents the output capacitor and the load. However, the capacitor voltage feedback cannot eliminate the high-frequency poles and the RHP zeros. These RHP zeros may be an impediment for high-bandwidth design if not properly treated. Based on the proposed model, these unwanted RHP zeros can be mitigated by either changing the resonant tank design or by proper feedback compensation. The accurate model is essential for a high-performance high-bandwidth LLC converter.
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    Adaptive bus voltage positioning for two-stage voltage regulators
    (United States Patent and Trademark Office, 2007-01-09)
    Alteration of voltage input to a voltage regulator output stage from a Vbus regulator stage in a two-stage voltage regulator provides optimal Vbus voltage placement for a wide range of current loads to increase voltage regulator efficiency and is particularly suited to CPUs having power-saving sleep modes of operation. An optimal voltage is selected or developed in response to information concerning operational mode or current consumption of the powered device. As a perfecting feature of one embodiment of the invention in which a discrete Vbus voltage is selected based on operational mode, the selected voltage is adjusted to further optimize the matching of the Vbus voltage placement to the load and provides a continuous range of voltages. In a second embodiment the entire Vbus positioning function is performed in response to current load information. A feed-forward arrangement is provided to avoid transient spikes as the Vbus voltage placement is altered.
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    Adaptive on-time control for power factor correction stage light load efficiency
    (United States Patent and Trademark Office, 2014-08-12)
    Light load efficiency of a power factor correction circuit is improved by adaptive on-time control and providing for selection between a continuous conduction mode and a discontinuous conduction mode wherein the discontinuous conduction mode increases time between switching pulses controlling connection of a cyclically varying voltage to a filter/inductor that delivers a desired DC voltage and thus can greatly reduce the switching frequency at light loads where switching frequency related losses dominate efficiency. The mode for controlling switching is preferably selected for each switching pulse within a half cycle of the cyclically varying input voltage. A multi-phase embodiment allows cancellation of EMI noise at harmonics of the switching frequency and adaptive change of phase angle allows for cancellation of dominant higher order harmonics as switching frequency is reduced.
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    Advanced Control Schemes for High-Bandwidth Multiphase Voltage Regulators
    Liu, Pei-Hsin (Virginia Tech, 2015-05-13)
    Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations. Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method. Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations. Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation. Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation. As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance.
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    Advanced Control Schemes for Voltage Regulators
    Lee, Kisun (Virginia Tech, 2008-03-28)
    The microprocessor faces a big challenge of heat dissipation. In order to enhance the performance of the microprocessor without increasing the heat dissipation, the leading microprocessor company, Intel, uses several methods to reduce the power consumption. Theses methods include enhanced sleep states control, the Speed Step technology, and multi-core architecture. These are closely related to the Voltage Regulator (VR), a dedicated power supply for the microprocessor and its control method. The speed of the VR control system should be high in order to meet the stringent load-line requirements with the high current and high di/dt, otherwise, a lot of decoupling capacitors are necessary. Capacitors make the VR cost and size higher. Therefore, the VR control method is very important. This dissertation discusses the way to increase the speed of VR without degrading other functions, such as the system efficiency, and the required control functions (AVP, current sharing and interleaving). The easiest way to increase the speed of the VR is to increase the switching frequency. However, higher switching frequency results in system efficiency degradation. This paper uses two approaches to deal with this issue. The first one is the architecture approach. The other is the fast transient control approach. For the architecture approach, a two-stage architecture is chosen. It is already shown that with a two-stage architecture, the switching frequency of the second stage can be increased, while keeping the same system efficiency. Therefore with the two-stage architecture, a high performance VR can be easily implemented. However, the light-load efficiency of two-stage architecture is not good because the bus voltage is designed for the full-load efficiency which is not optimized for the light load. The light-load efficiency is also important factor and it should be maximized because it is related to the battery life of mobile application or the energy utilization. Therefore, Adaptive Bus Voltage Positioning (ABVP) control has been proposed. By adaptively adjusting the bus voltage according to the load current, the system efficiency can be optimized for whole load range. The bus voltage rate of change is determined by the first stage bandwidth. In order to maintain regulation during a fast dynamic load, the first stage bandwidth should be high. However, it is observed from hardware when the first stage bandwidth is higher, the ABVP system can become unstable. To get a stable system, the first stage bandwidth is often designed to be slow which causes poor ABVP dynamic response. The large number of bus capacitors necessary for this also increases the size and cost. In this dissertation, in order to raise the first stage bandwidth, a stability analysis is performed. The instability loop (TABVP) is identified, and a small signal model to predict this loop is suggested. TABVP is related to the first stage bandwidth. With the higher first stage bandwidth, the peak magnitude of TABVP is larger. When the peak magnitude of TABVP touches 0dB, the system becomes unstable. Two solutions are proposed to reduce this TABVP magnitude without decreasing the first stage bandwidth. One method is to increase the feedforward gain and the other approach is to use a low pass filter. With these strategies, the ABVP system can be designed to be stable while pushing first stage bandwidth as high as possible. The ABVP-AVP system and its design are verified with hardware. For the fast transient control approach hysteretic control is chosen because of its fast transient and high light-load efficiency with DCM operation. However, in order to use the hysteretic control method for multiphase VR applications interleaving must be implemented. In this dissertation, a multiphase hysteretic control method is proposed which can achieve interleaving without losing its benefits. Using the phase locked loop (PLL), this control method locks the phase and frequency of the duty cycles to the reference clocks by modifying the size of the hysteretic band, to say, hysteretic band width. By phase shifting the reference clocks, interleaving can be achieved under steady state. During the load transient, the system loses the phase-locking function due to the slow hysteretic band width changing loop, and the system then reacts quickly to the load change without the interruption from the phase locking function (or the interleaving function). The proposed hysteretic control method consists of two loops, the fast hysteretic control loop and the slow hysteretic band width changing loop. These two nonlinear loops are difficult to model and analyze together. Therefore, assuming these two loops can be separated because of the speed difference, the phase plane model is used for the fast hysteretic control loop and the sampled data model is then used for the slow hysteretic band width changing loop. With these models, the proposed hysteretic control method can be analyzed and properly designed. However, if the transient occurs before the slow hysteretic band width changing loop settles down, the transient may start with the large hysteretic band width and the output voltage peak can exceed the specification. To prevent this, a hysteretic band width limiter is inserted. With the hardware, the proposed hysteretic control method and its design are verified. A two-phase VR with 300kHz switching frequency is built and the output capacitance required is only 860μF comparing to 1600μF output capacitance with the 50kHz bandwidth linear control method. That is about 46% capacitor reduction. The proposed hysteretic control method saturates the controller during the transient and the transient peak voltage is determined by the power stage parameters, the inductance and the output capacitors. By decreasing the inductance, the output capacitors are reduced. However, small inductance results in the low efficiency. In order to resolve this, the coupled inductor is used. With the coupled inductor, the transient inductance can be reduced with the same steady state inductance. Therefore, the transient speed can be faster without lowering down the system efficiency. The proposed hysteretic control method with the coupled inductor can be implemented using the DCR current sensing network. A two-phase VR with the proposed hysteretic control and the coupled inductor is built and the output capacitance is only 660μF comparing to 860μF output capacitance with the proposed hysteretic control only. A 23% capacitor reduction is achieved. And compared to the 50kHz bandwidth linear control method, a 60% capacitor reduction is achieved.
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    Advanced High-Frequency Electronic Ballasting Techniques for Gas Discharge Lamps
    Tao, Fengfeng (Virginia Tech, 2001-12-19)
    Small size, light weight, high efficacy, longer lifetime and controllable output are the main advantages of high-frequency electronic ballasts for gas discharge lamps. However, power line quality and electromagnetic interference (EMI) issues arise when a simple peak rectifying circuit is used. To suppress harmonic currents and improve power factor, input-current-shaping (ICS) or power-factor-correction (PFC) techniques are necessary. This dissertation addresses advanced high-frequency electronic ballasting techniques by using a single-stage PFC approach. The proposed techniques include single-stage boost-derived PFC electronic ballasts with voltage-divider-rectifier front ends, single-stage PFC electronic ballasts with wide range dimming controls, single-stage charge-pump PFC electronic ballasts with lamp voltage feedback, and self-oscillating single-stage PFC electronic ballasts. Single-stage boost-derived PFC electronic ballasts with voltage-divider-rectifier front ends are developed to solve the problem imposed by the high boost conversion ratio required by commonly used boost-derived PFC electronic ballast. Two circuit implementations are proposed, analyzed and verified by experimental results. Due to the interaction between the PFC stage and the inverter stage, extremely high bus-voltage stress may exist during dimming operation. To reduce the bus voltage and achieve a wide-range dimming control, a novel PFC electronic ballast with asymmetrical duty-ratio control is proposed. Experimental results show that wide stable dimming operation is achieved with constant switching frequency. Charge-pump (CP) PFC techniques utilize a high-frequency current source (CS) or voltage source (VS) or both to charge and discharge the so-called charge-pump capacitor in order to achieve PFC. The bulky DCM boost inductor is eliminated so that this family of PFC circuits has the potential for low cost and small size. A family of CPPFC electronic ballasts is investigated. A novel VSCS-CPPFC electronic ballast with lamp-voltage feedback is proposed to reduce the bus-voltage stress. This family of CPPFC electronic ballasts are implemented and evaluated, and verified by experimental results. To further reduce the cost and size, a self-oscillating technique is applied to the CPPFC electronic ballast. Novel winding voltage modulation and current injection concepts are proposed to modulate the switching frequency. Experimental results show that the self-oscillating CS-CPPFC electronic ballast with current injection offers a more cost-effective solution for non-dimming electronic ballast applications.
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    Advanced Integrated Single-Stage Power Factor Correction Techniques
    Zhang, Jindong (Virginia Tech, 2001-03-15)
    This dissertation presents the in-depth study and innovative solutions of the advanced integrated single-stage power-factor-correction (S2PFC) techniques, which target at the low- to medium-level power supplies, for wide range of applications, from power adapters and computers to various communication equipment. To limit the undesirable power converter input-current-harmonic's impact on the power line and other electronics equipment, stringent current harmonic regulations such as IEC 61000-3-2 have already been enforced. The S2PFC techniques have been proposed and intensively studied, in order to comply these regulations with minimal additional component count and cost. This dissertation provides a systematic study of the S2PFC input-current-shaping (ICS) mechanism, circuit topology generalization and variation, bulk capacitor voltage stress and switch current stress, converter design and optimization, and evaluation of the state-of-the-art S2PFC techniques with universal-line input. Besides, this presentation also presents the development of novel S2PFC techniques with a voltage-doubler-rectifier front end to both improve the performance and reduce the cost of S2PFC converters for (international voltage range) universal-line applications. The calculation and experimental results show that the proposed techniques offer a more cost-effective and efficient solution than industries' current practice, with universal-line input and converter power level up to 600 W. Finally, further improved technique is also presented with reduced filter inductor size and increased power density.
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    Advanced Single-Stage Power Factor Correction Techniques
    Qian, Jinrong (Virginia Tech, 1997-09-25)
    Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters. Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis. VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept. CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented. VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control. CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage.
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    Analysis and Comparison of Space Vector Modulation Schemes for Three-Leg and Four-Leg Voltage Source Inverters
    Prasad, V. Himamshu (Virginia Tech, 1997-05-15)
    Several space vector modulation schemes have been analyzed for three-leg and four-leg voltage source inverters. The analysis is performed with respect to a) switching losses, b) total harmonic distortion, c) peak-to-peak ripple in the line current and d) the ease of digital implementation. The analysis is performed over the entire range of modulation index and for varying load power factors (leading and lagging) under both balanced and unbalanced load conditions. The analysis shows that the performance of four-leg inverters is similar to three-leg inverters for various space vector modulation schemes. The analysis also verifies the fact that a modulation scheme with good harmonic performance usually has high switching losses and vice-versa. The analysis is verified using simulation and experiments. A novel algorithm for the calculation of total harmonic distortion of PWM signals has been proposed.
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    Analysis and design of a 500 kHz series resonant inverter for induction heating applications
    Grajales, Liliana (Virginia Tech, 1995-11-06)
    The steady state model and analysis of a phase-shift controlled series resonant inverter (PSC-SRl) is presented. This steady state model includes the evaluation of the zero-voltage switching (ZVS) condition and the determination of the ZVS operating region. Based upon this analysis a frequency control strategy that minimizes circulating energies is proposed. Also, a methodology to design the power stage components, and to predict the duty ratio and the operating frequency range is presented using a PSC-SRl design example operating at 500 kHz and 10 kW. In addition, a novel and simple frequency control circuit that implements the proposed frequency control strategy is provided. Besides, the analysis of the PSC-SRl complete power stage and two control-loop system (frequency control and duty ratio control) is given. Furthermore, the small-signal model and the compensation schemes for each of the control loops is presented. The analytical predictions are compared with experimental data measured from a 500 kHz, 10 kW laboratory prototype and conclusions are drawn.
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    Analysis and design of a low-ripple coupled-inductor boost topology
    Butler, Stephen J. (Virginia Tech, 1993-06-05)
    This thesis presents the development, analysis, and design of a new low-ripple coupled-inductor boost topology. This topology is proposed for applications in which the conventional boost requires an input filter and two-stage output filter. One "zero-ripple" coupled magnetic provides both energy storage and second-order filtering of the input and output currents. Dc analysis is presented along with design guidelines. A novel magnetic structure is proposed which simplifies design and manufacture, while improving reliability. Small signal models for the proposed topology are presented along with hardware verification. It is found that, with proper damping, the small signal characteristics of the coupled-inductor topology are very similar to those of the conventional boost. This new boost topology offers a compact alternative to the conventional boost without sacrificing performance.
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    Analysis and Design of High-Intensity-Discharge Lamp Ballast for Automotive Headlamp
    Hu, Yongxuan (Virginia Tech, 2001-11-19)
    The High-Intensity-Discharge Lamps (HID), consisting of a broad range of gas discharge lamps, are notable for their high luminous efficacy, good color rendering, and long life. Metal halide lamps have the best combination of the above properties and are considered the most ideal light sources. Recently, there has been an emerging demand to replace the conventional halogen headlamps with the newly introduced small-wattage metal halide HID lamps. However, this lamp demands a highly efficient ballast and very complex control circuitry that can achieve fast turn-on and different regulation modes during the lamp start-up process. Due to the complex lamp v-i profile and timing control requirements, control circuit built with conventional analog control is unavoidably cumbersome. With the unparalleled flexibility and programmability, digital control shows more advantages in this application. An automotive HID ballast with digital controller is developed to demonstrate the feasibility of the digital control along with some key issues in digital controller selection and design. Results show that the microcontroller-based HID ballast can successfully realize the required control functions and achieve a smooth turn-on process and a fast turn-on time of 8 seconds. One of the major issues of ballast design is the ballast/HID lamp system stability, which originates from the lamp negative incremental impedance. The lamp small-signal model is presented with simulation and measurements. The negative incremental impedance is attributed to a RHP zero in the small-signal model. A new analysis approach, impedance ratio criterion, is proposed to analyze the system stability. With this approach, it clearly shows how the control configurations and converter and control design affect the system stability. The results can provide guidance and be easily used in control configuration selection and converter and control design. Analysis shows that ballast based on PWM converter without inner current loop is unstable and with inner current loop can stabilized the system. This is the reason why for a microcontroller-based ballast system the inner current loop has to be used. HID lamp has its special acoustic resonance problem and thus a low-frequency unregulated full-bridge is used following the front-end DC/DC converter. To prevent from lamp re-igniting during each bridge commutation, a minimum current changing slope has to be guaranteed. In order to help design the converter, the ballast/lamp re-ignition analysis is presented. With this analysis, it shows that the output capacitance has to be small enough to ensure adequate current slope during zero crossing. Though some approximation is used to simplify the analysis, the results can provide qualitative guidance in the ballast design.
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    Analysis and design of microprocessor-controlled peak-power-tracking system
    Huynh, Phuong (Virginia Tech, 1992-05-14)
    Analyses and designs of a peak-power tracking system using microprocessor control are performed. Large-signal stability of the system for various modes of operation is analyzed to predict system dynamics. The stability analysis is supported mainly by qualitative graphical representations of different component blocks of the system. Small-signal stability analysis around the equilibrium points is done to assure proper performance and operation of this particular peak-power tracking system. Specific design details and procedures are discussed, and predictions from the analyses are verified through hardware.
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    Analysis and design of multiple-output forward converter with weighted voltage control
    Chen, Jing (Virginia Tech, 1994-02-09)
    This work presents the modeling and analyses of multiple-output forward converters with weighted voltage control. Based upon the analyses, the systematic design methodologies and design tools are provided. A power stage de model including all the major parasitics, which are detrimental to the output voltages, is derived. A nonlinear programming based design tool is developed to search for the weighting factors. Five methods of stacking secondaries to improve cross-regulation are presented, and the improvement of cross-regulation is quantified. A small-signal model of the multiple-output converters with coupled output filter inductors and weighted voltage control is established. The small-signal characteristics are studied, and the model shows that the system behavior is very sensitive to the coupling coefficient, which has been reported, but never been quantified. The pole-zero interlaced condition is derived. A current-mode control small-signal model is also presented, which can predict all the observed phenomena of current-mode control. Compensator design is discussed for different types of power stage transfer functions for both voltage-mode and current-mode control.
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    Analysis and Evaluation of Soft-switching Inverter Techniques in Electric Vehicle Applications
    Dong, Wei (Virginia Tech, 2003-04-22)
    This dissertation presents the systematic analysis and the critical assessment of the AC side soft-switching inverters in electric vehicle (EV) applications. Although numerous soft-switching inverter techniques were claimed to improve the inverter performance, compared with the conventional hard-switching inverter, there is the lack of comprehensive investigations of analyzing and evaluating the performance of soft-switching inverters. Starting with an efficiency comparison of a variety of the soft-switching inverters using analytical calculation, the dissertation first reveals the effects of the auxiliary circuit's operation and control on the loss reduction. Three types of soft-switching inverters realizing the zero-voltage-transition (ZVT) or zero-current-transition (ZCT) operation are identified to achieve high efficiency operation. Then one hard-switching inverter and the chosen soft-switching inverters are designed and implemented with the 55 kW power rating for the small duty EV application. The experimental evaluations on the dynamometer provide the accurate description of the performance of the soft-switching inverters in terms of the loss reductions, the electromagnetic interference (EMI) noise, the total harmonic distortion (THD) and the control complexity. An analysis of the harmonic distortion caused by short pulses is presented and a space vector modulation scheme is proposed to alleviate the effect. To effectively analyze the soft-switching inverters' performance, a simulation based electrical modeling methodology is developed. Not only it extends the EMI noise analysis to the higher frequency region, but also predicts the stress and the switching losses accurately. Three major modeling tasks are accomplished. First, to address the issues of complicated existing scheme, a new parameter extraction scheme is proposed to establish the physics-based IGBT model. Second, the impedance based measurement method is developed to derive the internal parasitic parameters of the half-bridge modules. Third, the finite element analysis software is used to develop the model for the laminated bus bar including the coupling effects of different phases. Experimental results from the single-leg operation and the three-phase inverter operation verify the effectiveness of the presented systematic electrical modeling approach. With the analytical tools verified by the testing results, the performance analysis is further extended to different power ratings and different bus voltage designs.
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    Analysis of Inductor-Coupled Zero-Voltage-Transition Converters
    Choi, Jae-Young (Virginia Tech, 2001-07-24)
    As is the case for DC-DC converters, multi-phase converters require both high-quality power control and high power-density. Although a higher switching frequency not only improves the quality of the converter output but also decreases the size of the converter, it increases switching losses and electromagnetic interference (EMI) noise. Since the soft-switching topologies reduce the switching losses of the converter main switches, the topologies make converters partially independent from the switching frequency. However, the conventional soft-switching topologies have already proposed most of the possible ways to improve converter performance. In addition, the trends of the newly generated power devices reduce the advantages of soft-switching topologies. This critical situation surrounding soft-switching topologies gives research motivations: What features of soft-switching topologies facilitate their practical applications? Given this motivation, the dissertation discusses two aspects = simplifying auxiliary circuits and accounting for the effects of soft-switching operations on the converter control. Engineers working with medium- and high-power multi-phase converters require simplified soft-switching topologies that have the same level of performance as the conventional soft-switching topologies. This demand is the impetus behind one of the research objectives = simplifying the auxiliary circuits of Zero-Voltage-Transition (ZVT) inverters. Simplifying the auxiliary circuits results in both a smaller number of and lower cost for auxiliary components, without any negative impact on performance. This dissertation proposes two major concepts for the simplification - the Single-Switch Single-Leg (S3L) ZVT cell and the Phase-Lock (PL) concept. Throughout an effort to eliminate circulating currents of inductor-coupled (IC) ZVT converters, the S3L ZVT cell is developed. The proposed cell allows a single auxiliary switch to achieve zero-voltage conditions for both the top and bottom main switches, and it achieves the same level of performance as the conventional ZVT cell, as well. This proposal makes IC ZVT topologies more attractive to multi-phase converter applications. Because all of the top main switches generally have identical sequences for zero-voltage turn-on commutations, one auxiliary switch might handle the commutations of all of the top main switches. This possibility introduces the PL concept, which allows the two auxiliary switches to provide a zero-voltage condition for any main switch commutation. In order to compensate for restrictions of this concept, a modified space-vector modulation (SVM) scheme also is introduced. A soft-switching topology changes the duty ratios of the converter, which affects the controllability of the converter. Therefore, this dissertation selects resolution of this issue as one of the research objectives. This dissertation derives the generalized timing equations of ZVT operations, and the generalized equations formulize the effect of ZVT operation on both duty ratios and DC current. Moreover, the effect of SVM schemes is also investigated. An average model of the ZVT converter is developed using both the timing analysis and the investigation of SVM schemes, and small-signal analysis using the average model predicts the steady-state characteristics of the converter.